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  • DRV8843 Dual H-Bridge Driver

    • SLVSAS8D April   2011  – November 2015 DRV8843

      PRODUCTION DATA.  

  • CONTENTS
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  • DRV8843 Dual H-Bridge Driver
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Motor Drivers
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bridge Control
      2. 7.4.2 Current Regulation
      3. 7.4.3 Decay Mode During Current Chopping
      4. 7.4.4 Blanking Time
      5. 7.4.5 nRESET and nSLEEP Operation
      6. 7.4.6 Protection Circuits
        1. 7.4.6.1 Overcurrent Protection (OCP)
        2. 7.4.6.2 Thermal Shutdown (TSD)
        3. 7.4.6.3 Undervoltage Lockout (UVLO)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Current Regulation
        2. 8.2.2.2 Decay Modes
        3. 8.2.2.3 Sense Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
    2. 9.2 Power Supply and Logic Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Thermal Protection
      2. 10.3.2 Power Dissipation
      3. 10.3.3 Heatsinking
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • PWP|28
    • MPDS373B
Thermal pad, mechanical data (Package|Pins)
  • PWP|28
    • PPTD124Q
Orderable Information
  • slvsas8d_oa
  • slvsas8d_pm
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DATA SHEET

DRV8843 Dual H-Bridge Driver

1 Features

  • Dual H-Bridge Motor Driver
    • Single/Dual Brushed DC
    • Stepper
  • IN/IN Control Interface
  • Optional Fixed Frequency Current Regulation
    • Two Bit Current control Allows Up to Four Current Levels
  • Low MOSFET On-Resistance
    • 2.5-A Maximum Drive Current at 24 V
      and TA = 25°C
    • Combined 400 mΩ RDS(ON) of High-Side and Low-Side at 24 V and TA = 25°C
  • 8.2-V to 45-V Operating Supply Voltage Range
  • Low Current Sleep Mode
  • Built-In 3.3-V Reference Output
  • Thermally Enhanced Surface Mount Package
  • Protection Features
    • Overcurrent Protection (OCP)
    • Thermal Shutdown (TSD)
    • Undervoltage Lockout (UVLO)
    • Fault Condition Indication Pin (nFAULT)

2 Applications

  • Printers
  • Scanners
  • Office Automation Machines
  • Gaming Machines
  • Factory Automation
  • Robotics

3 Description

The DRV8843 provides an integrated dual H-bridge motor driver solution for printers, scanners, and other automated equipment applications. The device can be used to drive one or two brushed DC motors, a bipolar stepper motor, or other loads. A simple PWM interface allows easy interfacing to controller circuits.

The output driver block consists of N-channel power MOSFETs configured as H-bridges. The DRV8843 an supply up to 2.5-A peak or 1.75-A RMS output current (with proper heat sinking at 24 V and
TA = 25°C) per H-bridge.

A low-power sleep mode is provided which shuts down internal circuitry to achieve very low quiescent current draw. This sleep mode can be set using a dedicated nSLEEP pin.

Internal protection features are provided for overtemperature, overcurrent, and undervoltage. Fault conditions are indicated by a nFAULT pin.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DRV8843 HTSSOP (28) 9.70 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

DRV8843 pg1_schematic_drv8843.gif

4 Revision History

Changes from C Revision (August 2013) to D Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo

5 Pin Configuration and Functions

PWP Package
28-Pin HTSSOP with PowerPAD™
Top View
DRV8843 po_drv8843.gif

Pin Functions

PIN I/O(1) DESCRIPTION EXTERNAL COMPONENTS
OR CONNECTIONS
NAME PIN
POWER AND GROUND
GND 14, 28 - Device ground
VMA 4 - Bridge A power supply Connect to motor supply (8.2 V to 45 V). Both pins must be connected to the same supply, bypassed with a 0.1-uF capacitor to GND, and connected to appropriate bulk capacitance.
VMB 11 - Bridge B power supply
V3P3OUT 15 O 3.3-V regulator output Bypass to GND with a 0.47-μF 6.3-V ceramic capacitor. Can be used to supply VREF.
CP1 1 IO Charge pump flying capacitor Connect a 0.01-μF 50-V capacitor between CP1 and CP2.
CP2 2 IO Charge pump flying capacitor
VCP 3 IO High-side gate drive voltage Connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ resistor to VM.
CONTROL
AIN1 21 I Bridge A input 1 Logic input controls state of AOUT1. Internal pulldown.
AIN2 20 I Bridge A input 2 Logic input controls state of AOUT2. Internal pulldown.
AI0 24 I Bridge A current set Sets bridge A current: 00 = 100%,
01 = 71%, 10 = 38%, 11 = 0
Internal pulldown.
AI1 25 I
BIN1 22 I Bridge B input 1 Logic input controls state of BOUT1. Internal pulldown.
BIN2 23 I Bridge B input 2 Logic input controls state of BOUT2. Internal pulldown.
BI0 26 I Bridge B current set Sets bridge B current: 00 = 100%,
01 = 71%, 10 = 38%, 11 = 0
Internal pulldown.
BI1 27 I
DECAY 19 I Decay mode Low = slow decay, open = mixed decay,
high = fast decay
Internal pulldown and pullup.
nRESET 16 I Reset input Active-low reset input initializes internal logic and disables the H-bridge outputs. Internal pulldown.
nSLEEP 17 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode. Internal pulldown.
AVREF 12 I Bridge A current set reference input Reference voltage for winding current set. Can be driven individually with an external DAC for microstepping, or tied to a reference (e.g., V3P3OUT).
BVREF 13 I Bridge B current set reference input
STATUS
nFAULT 18 OD Fault Logic low when in fault condition (overtemp, overcurrent)
OUTPUT
ISENA 6 IO Bridge A ground / Isense Connect to current sense resistor for bridge A
ISENB 9 IO Bridge B ground / Isense Connect to current sense resistor for bridge B
AOUT1 5 O Bridge A output 1 Connect to motor winding A
AOUT2 7 O Bridge A output 2
BOUT1 10 O Bridge B output 1 Connect to motor winding B
BOUT2 8 O Bridge B output 2
(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
Power supply voltage range VMx –0.3 47 V
Power supply ramp rate VMx 1 V/µs
Digital pin voltage range –0.5 7 V
Input voltage VREF –0.3 4 V
ISENSEx pin voltage(3) –0.8 0.8 V
Peak motor drive output current, t < 1 μS Internally limited A
Continuous motor drive output current(4) 0 2.5 A
Continuous total power dissipation See Thermal Information.
Operating virtual junction temperature range, TJ –40 150 °C
Operating ambient temperature range, TA –40 85 °C
Storage Temperature, TSTG –60 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Transients of ±1 V for less than 25 ns are acceptable.
(4) Power dissipation and thermal limits must be observed.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VM Motor power supply voltage range(1) 8.2 45 V
VREF VREF input voltage(2) 1 3.5 V
IV3P3 V3P3OUT load current 0 1 mA
fPWM Externally applied PWM frequency 0 100 kHz
(1) All VM pins must be connected to the same supply voltage.
(2) Operational at VREF between 0 V and 1 V, but accuracy is degraded.

6.4 Thermal Information

THERMAL METRIC(1) DRV8843 UNIT
PWP (HTSSOP)
28 PINS
RθJA Junction-to-ambient thermal resistance 31.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 15.9 °C/W
RθJB Junction-to-board thermal resistance 5.6 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 5.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVM VM operating supply current VM = 24 V, fPWM < 50 kHz 5 8 mA
IVMQ VM sleep mode supply current VM = 24 V 10 20 μA
VUVLO VM undervoltage lockout voltage VM rising 7.8 8.2 V
V3P3OUT REGULATOR
V3P3 V3P3OUT voltage IOUT = 0 to 1 mA 3.2 3.3 3.4 V
LOGIC-LEVEL INPUTS
VIL Input low voltage 0.6 0.7 V
VIH Input high voltage 2.2 5.25 V
VHYS Input hysteresis 0.3 0.45 0.6 V
IIL Input low current VIN = 0 –20 20 μA
IIH Input high current VIN = 3.3 V 100 μA
RPD Internal pulldown resistance 100 kΩ
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL Output low voltage IO = 5 mA 0.5 V
IOH Output high leakage current VO = 3.3 V 1 μA
DECAY INPUT
VIL Input low threshold voltage For slow decay (brake) mode 0 0.8 V
VIH Input high threshold voltage For fast decay (coast) mode 2 V
IIN Input current ±40 μA
RPU Internal pullup resistance (to 3.3 V) 130 kΩ
RPD Internal pulldown resistance 80 kΩ
H-BRIDGE FETS
RDS(ON) HS FET on resistance VM = 24 V, IO = 1 A, TJ = 25°C 0.2 Ω
VM = 24 V, IO = 1 A, TJ = 85°C 0.25 0.32
LS FET on resistance VM = 24 V, IO = 1 A, TJ = 25°C 0.2
VM = 24 V, IO = 1 A, TJ = 85°C 0.25 0.32
IOFF Off-state leakage current –20 20 μA
MOTOR DRIVER
fPWM Internal current control PWM frequency 50 kHz
tBLANK Current sense blanking time 3.75 μs
tR Rise time 30 200 ns
tF Fall time 30 200 ns
PROTECTION CIRCUITS
IOCP Overcurrent protection trip level 3 A
tTSD Thermal shutdown temperature Die temperature 150 160 180 °C
CURRENT CONTROL
IREF VREF input current VREF = 3.3 V –3 3 μA
VTRIP xISENSE trip voltage xVREF = 3.3 V, 100% current setting 635 660 685 mV
xVREF = 3.3 V, 71% current setting 445 469 492
xVREF = 3.3 V, 38% current setting 225 251 276
AISENSE Current sense amplifier gain Reference only 5 V/V

6.6 Typical Characteristics

DRV8843 D001_SLVSA73.gif
Figure 1. IVMx vs V(VMx)
DRV8843 D003_SLVSA73.gif
Figure 3. RDS(ON) vs V(VMx)
DRV8843 D002_SLVSA73.gif
Figure 2. IVMxQ vs V(VMx)
DRV8843 D004_SLVSA73.gif
Figure 4. RDS(ON) vs Temperature

 
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