SLLSEK2A June   2014  – March 2017 DRV8846

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Motor Drivers
      2. 7.3.2 Micro-Stepping Indexer
      3. 7.3.3 Current Regulation
      4. 7.3.4 Decay Mode
      5. 7.3.5 Blanking Time
      6. 7.3.6 Protection Circuits
        1. 7.3.6.1 Overcurrent Protection (OCP)
        2. 7.3.6.2 Thermal Shutdown (TSD)
        3. 7.3.6.3 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Device Functional Modes

The DRV8846 device is active unless the nSLEEP pin is driven low. In sleep mode, the VINT regulator is disabled and the H-bridge FETs are disabled (Hi-Z). The time tSLEEP must elapse after a falling edge on the nSLEEP pin before the device enters sleep mode. The DRV8846 is brought out of sleep mode by bringing the nSLEEP pin high. The time tWAKE must elapse, after nSLEEP is brought high, before the outputs change state.

If the nENBL pin is brought high, the H-bridge outputs are disabled, but the internal logic is still active. An appropriate edge on STEP (depending on the step mode) advances the indexer, but the outputs do not change state until nENBL is driven low.

Table 10. Operating Modes

Mode Condition H-Bridge VINT Indexer
Operating 4 V < VM < 18 V
nSLEEP pin = 1
nENBL = 0		 Operating Operating Operating
Disabled 4 V < VM < 18 V
nSLEEP pin = 1
nENBL = 1		 Disabled Operating Operating
Sleep 4 V < VM < 18 V
nSLEEP pin = 0		 Disabled Disabled Disabled
Fault Any fault condition met Disabled Depends on fault Depends on fault