SLVSE65C July   2018  – December 2023 DRV8847

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Motor Drivers
      2. 7.3.2 Bridge Operation
        1. 7.3.2.1 Forward Operation
        2. 7.3.2.2 Reverse Operation
        3. 7.3.2.3 Coast Operation (Fast Decay)
        4. 7.3.2.4 Brake Operation (Slow Decay)
      3. 7.3.3 Bridge Control
        1. 7.3.3.1 4-Pin Interface
        2. 7.3.3.2 2-Pin Interface
        3. 7.3.3.3 Parallel Bridge Interface
        4. 7.3.3.4 Independent Bridge Interface
      4. 7.3.4 Current Regulation
      5. 7.3.5 Current Recirculation and Decay Modes
      6. 7.3.6 Torque Scalar
      7. 7.3.7 Stepping Modes
        1. 7.3.7.1 Full-Stepping Mode (4-Pin Interface)
        2. 7.3.7.2 Full-Stepping Mode (2-Pin Interface)
        3. 7.3.7.3 Half-Stepping Mode (With Non-Driving Fast Decay)
        4. 7.3.7.4 Half-Stepping Mode (With Non-Driving Slow Decay)
      8. 7.3.8 Motor Driver Protection Circuits
        1. 7.3.8.1 Overcurrent Protection (OCP)
          1. 7.3.8.1.1 OCP Automatic Retry (Hardware Device and Software Device (OCPR = 0b))
          2. 7.3.8.1.2 OCP Latch Mode (Software Device (OCPR = 1b))
          3. 7.3.8.1.3 42
        2. 7.3.8.2 Thermal Shutdown (TSD)
        3. 7.3.8.3 VM Undervoltage Lockout (VM_UVLO)
        4. 7.3.8.4 Open Load Detection (OLD)
          1. 7.3.8.4.1 Full-Bridge Open Load Detection
          2. 7.3.8.4.2 Load Connected to VM
          3. 7.3.8.4.3 Load Connected to GND
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 I2C Communication
        1. 7.5.1.1 I2C Write
        2. 7.5.1.2 I2C Read
      2. 7.5.2 Multi-Slave Operation
    6. 7.6 Register Map
      1. 7.6.1 Slave Address Register (Address = 0x00) [reset = 0x60]
      2. 7.6.2 IC1 Control Register (Address = 0x01) [reset = 0x00]
      3. 7.6.3 IC2 Control Register (Address = 0x02) [reset = 0x00]
      4. 7.6.4 Slew-Rate and Fault Status-1 Register (Address = 0x03) [reset = 0x40]
      5. 7.6.5 Fault Status-2 Register (Address = 0x04) [reset = 0x00]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Stepper Motor Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Stepping Modes
            1. 8.2.1.2.1.1 Full-Stepping Operation
            2. 8.2.1.2.1.2 Half-Stepping Operation with Fast Decay
            3. 8.2.1.2.1.3 Half-Stepping Operation with Slow Decay
          2. 8.2.1.2.2 Current Regulation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Dual BDC Motor Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Motor Voltage
          2. 8.2.2.2.2 Current Regulation
          3. 8.2.2.2.3 Sense Resistor
      3. 8.2.3 Open Load Implementation
        1. 8.2.3.1 Open Load Detection Circuit
        2. 8.2.3.2 OLD for Ground Connected Load
          1. 8.2.3.2.1 Half Bridge Open
          2. 8.2.3.2.2 Half Bridge Short
          3. 8.2.3.2.3 Load Connected
        3. 8.2.3.3 OLD for Supply (VM) Connected Load
          1. 8.2.3.3.1 Half Bridge Open
          2. 8.2.3.3.2 Half Bridge Short
          3. 8.2.3.3.3 Load Connected
        4. 8.2.3.4 OLD for Full Bridge Connected Load
          1. 8.2.3.4.1 Full Bridge Open
            1. 8.2.3.4.1.1 High side comparator of half-bridge-1 (OL1_HS)
            2. 8.2.3.4.1.2 Low side comparator of half-bridge-2 (OL2_LS)
          2. 8.2.3.4.2 Full Bridge Short
            1. 8.2.3.4.2.1 High side comparator of half-bridge-1 (OL1_HS)
            2. 8.2.3.4.2.2 Low side comparator of half-bridge-2 (OL2_LS)
          3. 8.2.3.4.3 Load Connected in Full Bridge
            1. 8.2.3.4.3.1 High side comparator of half-bridge-1 (OL1_HS)
            2. 8.2.3.4.3.2 Low side comparator of half-bridge-2 (OL2_LS)
  10.   Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  11. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
      1. 9.3.1 Maximum Output Current
      2. 9.3.2 Thermal Protection
    4. 9.4 Power Dissipation
  12. 10Device and Documentation Support
    1. 10.1 Device Support (Optional)
      1. 10.1.1 Development Support (Optional)
      2. 10.1.2 Device Nomenclature (Optional)
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
  13. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • PWP|16
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 12 V.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES (VM)
IVMVM operating supply currentVM = 2.7 V; nSLEEP = 1; INX = 022.5mA
VM = 5 V; nSLEEP = 1; INX = 033.5mA
VM = 12 V; nSLEEP = 1; INX = 033.5mA
IVMQVM sleep mode currentVM = 2.7 V; nSLEEP = 0; TA = 25°C0.1µA
VM = 2.7 V; nSLEEP = 0; TA = 85°C0.5µA
VM = 5 V; nSLEEP = 0; TA = 25°C0.2µA
VM = 5 V; nSLEEP = 0; TA = 85°C1µA
VM = 12 V; nSLEEP = 0; TA = 25°C1.7µA
VM = 12 V; nSLEEP = 0; TA = 85°C2.5µA
tSLEEPSleep timenSLEEP = 0 to sleep mode2µs
tWAKEWake-up timenSLEEP = 1 to output transition1.5ms
tONTurnon-timeVM > UVLO to output transition (nSLEEP = 1)1.5ms
LOGIC-LEVEL INPUTS (IN1, IN2, IN3, IN4, NSLEEP, TRQ, SCL, SDA)
VILInput logic low voltageVM < 7 V00.6V
VM >= 7 V (1)01.0V
VIHInput logic high voltage1.65.5V
VHYSInput logic hysteresisnSLEEP pin40mV
VHYSInput logic hysteresisIN1, IN2, IN3, IN4, TRQ, SCL pins100mV
VILnSLEEP00.6V
VIHnSLEEP1.65.5V
VHYSnSLEEP40mV
IILInput logic low currentVIN = 0 V-11µA
IIHInput logic high currentIN1, IN2, IN3, IN4, TRQ, VIN = 5 V1835µA
nSLEEP, VIN = minimum (VM, 5 V)1025µA
tPDPropagation DelayINx edge to output100400600ns
tDEGLITCHInput logic deglitch50ns
TRI-LEVEL INPUTS (MODE)
VILTri-level input logic low voltage00.6V
VIZTri-level input hi-Z voltage1.2V
VIHTri-level input logic high voltage1.65.5V
IILTri-level input logic low currentVIN = 0 V-9-4µA
IIHTri-level input logic high currentVIN = 5 V825µA
OPEN-DRAIN OUTPUTS (nFAULT)
VOLOutput logic low voltageIOD = 5 mA0.5V
IOHOutput logic high currentVOD = 3.3 V-11µA
OPEN-DRAIN OUTPUTS (SDA)
VOLOutput logic low voltageIOD = 5 mA0.5V
IOHOutput logic high currentVOD = 3.3 V-11µA
CBCapacitive load for each bus line400pF
DRIVER OUTPUTS (OUT1, OUT2, OUT3, OUT4)
RDS(ON)_HSHigh-side MOSFET on resistanceVVM = 2.7 V; IOUT = 0.5 A; TA = 25°C690mΩ
VVM = 2.7 V; IOUT = 0.5 A; TA = 85°C950mΩ
VVM = 5 V; IOUT = 0.5 A; TA = 25°C530mΩ
VVM = 5 V; IOUT = 0.5 A; TA = 85°C740mΩ
VVM = 12 V; IOUT = 0.5 A; TA = 25°C520mΩ
VVM = 12 V; IOUT = 0.5 A; TA = 85°C700mΩ
RDS(ON)_LSLow-side MOSFET on resistanceVVM = 2.7 V; IOUT = 0.5 A; TA = 25°C570mΩ
VVM = 2.7 V; IOUT = 0.5 A; TA = 85°C900mΩ
VVM = 5 V; IOUT = 0.5 A; TA = 25°C460mΩ
VVM = 5 V; IOUT = 0.5 A; TA = 85°C690mΩ
VVM = 12 V; IOUT = 0.5 A; TA = 25°C450mΩ
VVM = 12 V; IOUT = 0.5 A; TA = 85°C680mΩ
IOFFOff-state leakage currentVVM = 5 V; TJ = 25 °C; VOUT = 0 V-11µA
tRISEOutput rise timeVVM = 12 V; IOUT = 0.5 A150ns
tFALLOutput fall timeVVM = 12 V, IOUT = 0.5 A150ns
tDEADOutput dead timeInternal dead time200ns
VSDBody diode forward voltageIOUT = 0.5 A1.1V
PWM CURRENT CONTROL (ISEN12, SEN34)
VTRIPISENxx trip voltageTorque at 100% (TRQ = 0)140150160mV
Torque at 50% (TRQ = 1)63.757586.25mV
tBLANKCurrent sense blanking time1.8µs
tOFFCurrent control constant off time20µs
PROTECTION CIRCUITS
VUVLOSupply undervoltage lockoutSupply rising2.7V
Supply falling2.4V
VUVLO_HYSSupply undervoltage hysteresisRising to falling theshold50mV
tUVLOSupply undervoltage deglitch timeVM falling; UVLO report10µs
IOCPOvercurrent protection trip point (2)1.62A
tOCPOvercurrent protection deglitch timeVVM < 15 V3µs
VVM >= 15 V1µs
tRETRYOvercurrent protection retry time1ms
IOL_PUOpen load pull up current< 15 nF on OUTx Pin, VVM = 2.7 V100µA
IOL_PUOpen load pull-up current< 15 nF on OUTx Pin200µA
IOL_PDOpen load pull down current< 15 nF on OUTx Pin, VVM = 2.7 V130µA
IOL_PDOpen load pull-down current< 15 nF on OUTx Pin230µA
IOLOpen load pull up and pull down current230µA
VOL_HSOpen load detect threshold (high side)VVM = 2.7 V1.3V
VOL_HSOpen load detect threshold (high side)2.3V
VOL_LSOpen load detect threshold (low side)VVM = 2.7 V0.67V
VOL_LSOpen load detect threshold (low side)1.2V
VOLOpen load detect threshold voltage 1.1V
TTSDThermal shutdown temperature150160180°C
THYSThermal shutdown hysteresis40°C
Vb_BJT_27CBase voltage of BJT in OTS (Testpad out at 12V supply)
(1) Specified by design and characterization
(2) For VM > 16.5 V, the output current on OUTx must be limited to 4 A