SLLSEL7B October   2014  – April 2024 DRV8848

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
    2.     External Components
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Comm
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 PWM Motor Drivers
      2. 6.3.2 Bridge Control
      3. 6.3.3 Parallel Operation
      4. 6.3.4 Current Regulation
      5. 6.3.5 Current Recirculation and Decay Modes
      6. 6.3.6 Protection Circuits
        1. 6.3.6.1 OCP
        2. 6.3.6.2 TSD
        3. 6.3.6.3 UVLO
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Current Regulation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance Sizing
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
    6. 8.6 Community Resources
    7. 8.7 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Device Functional Modes

The DRV8848 is active unless the nSLEEP pin is brought logic low. In sleep mode, the VINT regulator is disabled and the H-bridge FETs are disabled Hi-Z. Note that tSLEEP must elapse after a falling edge on the nSLEEP pin before the device is in sleep mode. The DRV8848 is brought out of sleep mode automatically if nSLEEP is brought logic high. Note that tWAKE must elapse before the output change state after wake-up.

When VVM falls below the VM UVLO threshold (VUVLO), the output driver, internal logic, and VINT regulator are reset.

Table 6-3 Functional Modes
MODECONDITIONH-BRIDGEVINT
Operating4V < VVM < 18V
nSLEEP pin = 1		OperatingOperating
Sleep4V < VVM < 18V
nSLEEP pin = 0		DisabledDisabled
FaultAny fault condition metDisabledDepends on fault