SLLSEL7B October   2014  – April 2024 DRV8848

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
    2.     External Components
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Comm
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 PWM Motor Drivers
      2. 6.3.2 Bridge Control
      3. 6.3.3 Parallel Operation
      4. 6.3.4 Current Regulation
      5. 6.3.5 Current Recirculation and Decay Modes
      6. 6.3.6 Protection Circuits
        1. 6.3.6.1 OCP
        2. 6.3.6.2 TSD
        3. 6.3.6.3 UVLO
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Current Regulation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance Sizing
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
    6. 8.6 Community Resources
    7. 8.7 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.2 Bridge Control

Table 6-1 shows the logic for the inputs xIN1 and xIN2.

Table 6-1 Bridge Control
xIN1xIN2xOUT1xOUT2Function (DC Motor)
00ZZCoast (fast decay)
01LHReverse
10HLForward
11LLBrake (slow decay)

Note:

Pins AIN1 and AIN2 are tri-level, so when the pins are left Hi-Z, the pins are not internally pulled to logic low. When AIN1 or AIN2 are set to Hi-Z and not in parallel mode, the output driver maintains the previous state.