SLVSDY7B October 2017 – January 2021 DRV8873-Q1
PRODUCTION DATA
If at any time the voltage on the VM pin falls below the UVLO-threshold voltage, V(UVLO), for the voltage supply, all the outputs (OUTx) are disabled, and the nFAULT pin is driven low. The charge pump is disabled in this condition. The FAULT and UVLO bits are latched high in the SPI registers. Normal operation resumes (motor-driver operation and nFAULT released) when the VM undervoltage condition is removed. The UVLO bit remains set until it is cleared through the CLR_FLT bit or an nSLEEP reset pulse.
During the power-up sequence VM must exceed V(UVLO) recovery max limit in order to power-up and function properly. After a successful power-up sequence, the device can operate down to the V(UVLO) report limit before going into the undervoltage lockout condition.