SLVSET1 August   2018 DRV8873

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control
        1. 7.3.1.1 Control Modes
        2. 7.3.1.2 Half-Bridge Operation
        3. 7.3.1.3 Internal Current Sense and Current Regulation
        4. 7.3.1.4 Slew-Rate Control
        5. 7.3.1.5 Dead Time
        6. 7.3.1.6 Propagation Delay
        7. 7.3.1.7 nFAULT Pin
        8. 7.3.1.8 nSLEEP as SDO Reference
      2. 7.3.2 Motor Driver Protection Circuits
        1. 7.3.2.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.2.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.2.3 Overcurrent Protection (OCP)
          1. 7.3.2.3.1 Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.2.3.2 Automatic Retry (OCP_MODE = 01b)
          3. 7.3.2.3.3 Report Only (OCP_MODE = 10b)
          4. 7.3.2.3.4 Disabled (OCP_MODE = 11b)
        4. 7.3.2.4 Open-Load Detection (OLD)
          1. 7.3.2.4.1 Open-Load Detection in Passive Mode (OLP)
          2. 7.3.2.4.2 Open-Load Detection in Active Mode (OLA)
        5. 7.3.2.5 Thermal Shutdown (TSD)
          1. 7.3.2.5.1 Latched Shutdown (TSD_MODE = 0b)
          2. 7.3.2.5.2 Automatic Recovery (TSD_MODE = 1b)
        6. 7.3.2.6 Thermal Warning (OTW)
      3. 7.3.3 Hardware Interface
        1. 7.3.3.1 MODE (Tri-Level Input)
        2. 7.3.3.2 Slew Rate
    4. 7.4 Device Functional Modes
      1. 7.4.1 Motor Driver Functional Modes
        1. 7.4.1.1 Sleep Mode (nSLEEP = 0)
        2. 7.4.1.2 Disable Mode (nSLEEP = 1, DISABLE = 1)
        3. 7.4.1.3 Operating Mode (nSLEEP = 1, DISABLE = 0)
        4. 7.4.1.4 nSLEEP Reset Pulse
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI) Communication
        1. 7.5.1.1 SPI Format
        2. 7.5.1.2 SPI for a Single Slave Device
        3. 7.5.1.3 SPI for Multiple Slave Devices in Parallel Configuration
        4. 7.5.1.4 SPI for Multiple Slave Devices in Daisy Chain Configuration
    6. 7.6 Register Maps
      1. 7.6.1 Status Registers
        1. 7.6.1.1 FAULT Status Register Name (address = 0x00)
          1. Table 21. FAULT Status Register Field Descriptions
        2. 7.6.1.2 DIAG Status Register Name (address = 0x01)
          1. Table 22. DIAG Status Register Field Descriptions
      2. 7.6.2 Control Registers
        1. 7.6.2.1 IC1 Control Register (address = 0x02)
          1. Table 24. IC1 Control Register Field Descriptions
        2. 7.6.2.2 IC2 Control Register (address = 0x03)
          1. Table 25. IC2 Control Register Field Descriptions
        3. 7.6.2.3 IC3 Control Register (address = 0x04)
          1. Table 26. IC3 Control Register Field Descriptions
        4. 7.6.2.4 IC4 Control Register (address = 0x05)
          1. Table 27. IC4 Control Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Motor Voltage
        2. 8.2.1.2 Drive Current and Power Dissipation
        3. 8.2.1.3 Sense Resistor
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Thermal Considerations
        2. 8.2.2.2 Heatsinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1.3 Internal Current Sense and Current Regulation

The IPROPI pin outputs an analog current that is proportional to the current flowing in the H-bridge. The output current is typically 1/1100 of the current in both high-side FETs. The IPROPI pin is derived from the current through either of the high-side FETs. Because of this, the IPROPI pin does not represent the half bridge current when operating in a fast decay mode or low-side slow decay mode. The IPROPI pin represents the H-bridge current under forward drive, reverse drive, and high-side slow decay. The IPROPI output is delayed by approximately 2 µs for the fastest slew-rate setting (43.2 V/µs) after the high-side FET is switched on.

DRV8873 drv8873q1_current_sense_block_diagr.gifFigure 12. Current-Sense Block Diagram

The selection of the external resistor should be such that the voltage on the IPROPI pin is less than 5 V. Therefore the resistor must be sized less than this value based on Equation 1. The range of current that can be monitored is from 100 mA to 10 A assuming the selected external resistor meets the calculated value from Equation 1. If the current exceeds 10 A, the device could reach overcurrent protection (OCP) or overtemperature shutdown (TSD). If OCP occurs, the device disables the internal MOSFETs and protects itself (for the hardware version of the device) or based on the OCP_MODE setting (for the SPI version of the device). For guidelines on selecting a sense resistor, see the Sense Resistor section.

Equation 1. R(SENSE) = k × 5 V / IO

where

  • k is the current mirror scaling factor, which is typically 1100.
  • IO is the maximum drive current to be monitored.

NOTE

Texas Instruments recommends the load current not exceed 8 A during normal operation. If slew rate setting of 2.6 V/µs (SR = 111b) is used when the load current is about 8 A, choose TOFF to be either 40 µs or 60 µs.

The SPI version of the device limits the output current based on the trip level set in the SPI registers. In the hardware version of the device, the current trip limit is set to 6.5 A. The current regulation feature is enabled by default on both the outputs (OUT1 and OUT2). To disable current regulation in the hardware version of the device, the nITRIP pin must be connected to DVDD. To disable current regulation in the SPI version of the device, the DIS_ITRIP bits in the IC4 Control register must be written to. The bit settings are:

  • 01b to disable current regulation only on the OUT1 pin
  • 10b to disable current regulation only on the OUT2 pin
  • 11b to disable current regulation on both the OUT1 and OUT2 pins

Table 8. Control Regulation Threshold

PARAMETER ITRIP_LVL BIT MIN TYP MAX UNIT
ITRIP Current limit threshold ITRIP_LVL = 00b 3.4 4 4.6 A
ITRIP_LVL = 01b 4.6 5.4 6.2 A
ITRIP_LVL = 10b 5.5 6.5 7.5 A
ITRIP_LVL = 11b 6 7 8 A

When the ITRIP current has been reached, the device enforces slow current decay by enabling both the high-side FETs for a time of tOFF . In the hardware version of the device, the tOFF time is 40 µs. The tOFF time is selectable through SPI in the SPI version of the device, as shown in Table 9. The default setting is 01b (tOFF = 40 µs).

Table 9. PWM Off Time Settings

PARAMETER TOFF BIT tOFF DURATION UNIT
tOFF PWM off time TOFF = 00b 20 µs
TOFF = 01b 40 µs
TOFF = 10b 60 µs
TOFF = 11b 80 µs
DRV8873 drv8873-q1-itrip.gifFigure 13. Current Regulation Time Periods

When the tOFF time has elapsed and the current level falls below the current regulation (ITRIP) level, the output is re-enabled according to the inputs. If, after the tOFF time has elapsed the current is still higher than the ITRIP level, the device enforces another tOFF time period of the same duration.

The drive time (tDRIVE) occurs until another ITRIP event is reached and depends heavily on the VM voltage, the back-EMF of the motor, and the inductance of the motor. During the tDRIVE time, the current-sense regulator does not enforce the ITRIP limit until the tBLANK time has elapsed. While in current regulation, the inputs can be toggled to drive the load in the opposite direction to decay the current faster. For example, if the load was in forward drive prior to entering current regulation it can only go into reverse drive when the driver enforces current regulation.

The IPROPI1 pin represents the current flowing through the HS1 MOSFET of half-bridge 1. The IPROPI2 pin represents the current flowing through the HS2 MOSFET of half-bridge 2. To measure current with one sense resistor, the IPROPI1 and IPROPI2 pins must be connected together with the RSENSE resistor as shown in Figure 14. In this configuration, the current-sense output is proportional to the sum of the currents flowing through the both high-side FETs.

DRV8873 drv8873q1_current_sense_output.gifFigure 14. Current Sense Output