SLVSET1
August 2018
DRV8873
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Simplified Schematic
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
SPI Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Bridge Control
7.3.1.1
Control Modes
7.3.1.2
Half-Bridge Operation
7.3.1.3
Internal Current Sense and Current Regulation
7.3.1.4
Slew-Rate Control
7.3.1.5
Dead Time
7.3.1.6
Propagation Delay
7.3.1.7
nFAULT Pin
7.3.1.8
nSLEEP as SDO Reference
7.3.2
Motor Driver Protection Circuits
7.3.2.1
VM Undervoltage Lockout (UVLO)
7.3.2.2
VCP Undervoltage Lockout (CPUV)
7.3.2.3
Overcurrent Protection (OCP)
7.3.2.3.1
Latched Shutdown (OCP_MODE = 00b)
7.3.2.3.2
Automatic Retry (OCP_MODE = 01b)
7.3.2.3.3
Report Only (OCP_MODE = 10b)
7.3.2.3.4
Disabled (OCP_MODE = 11b)
7.3.2.4
Open-Load Detection (OLD)
7.3.2.4.1
Open-Load Detection in Passive Mode (OLP)
7.3.2.4.2
Open-Load Detection in Active Mode (OLA)
7.3.2.5
Thermal Shutdown (TSD)
7.3.2.5.1
Latched Shutdown (TSD_MODE = 0b)
7.3.2.5.2
Automatic Recovery (TSD_MODE = 1b)
7.3.2.6
Thermal Warning (OTW)
7.3.3
Hardware Interface
7.3.3.1
MODE (Tri-Level Input)
7.3.3.2
Slew Rate
7.4
Device Functional Modes
7.4.1
Motor Driver Functional Modes
7.4.1.1
Sleep Mode (nSLEEP = 0)
7.4.1.2
Disable Mode (nSLEEP = 1, DISABLE = 1)
7.4.1.3
Operating Mode (nSLEEP = 1, DISABLE = 0)
7.4.1.4
nSLEEP Reset Pulse
7.5
Programming
7.5.1
Serial Peripheral Interface (SPI) Communication
7.5.1.1
SPI Format
7.5.1.2
SPI for a Single Slave Device
7.5.1.3
SPI for Multiple Slave Devices in Parallel Configuration
7.5.1.4
SPI for Multiple Slave Devices in Daisy Chain Configuration
7.6
Register Maps
7.6.1
Status Registers
7.6.1.1
FAULT Status Register Name (address = 0x00)
Table 21.
FAULT Status Register Field Descriptions
7.6.1.2
DIAG Status Register Name (address = 0x01)
Table 22.
DIAG Status Register Field Descriptions
7.6.2
Control Registers
7.6.2.1
IC1 Control Register (address = 0x02)
Table 24.
IC1 Control Register Field Descriptions
7.6.2.2
IC2 Control Register (address = 0x03)
Table 25.
IC2 Control Register Field Descriptions
7.6.2.3
IC3 Control Register (address = 0x04)
Table 26.
IC3 Control Register Field Descriptions
7.6.2.4
IC4 Control Register (address = 0x05)
Table 27.
IC4 Control Register Field Descriptions
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Motor Voltage
8.2.1.2
Drive Current and Power Dissipation
8.2.1.3
Sense Resistor
8.2.2
Detailed Design Procedure
8.2.2.1
Thermal Considerations
8.2.2.2
Heatsinking
8.2.3
Application Curves
9
Power Supply Recommendations
9.1
Bulk Capacitance Sizing
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Community Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
12.1
Package Option Addendum
12.1.1
Packaging Information
12.1.2
Tape and Reel Information
Package Options
Mechanical Data (Package|Pins)
PWP|24
MPDS372A
Thermal pad, mechanical data (Package|Pins)
PWP|24
PPTD264C
Orderable Information
slvset1_oa
7.5
Programming