SLVSF66A August   2019  – December  2019 DRV8874

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Control Modes
        1. 7.3.2.1 PH/EN Control Mode (PMODE = Logic Low)
        2. 7.3.2.2 PWM Control Mode (PMODE = Logic High)
        3. 7.3.2.3 Independent Half-Bridge Control Mode (PMODE = Hi-Z)
      3. 7.3.3 Current Sense and Regulation
        1. 7.3.3.1 Current Sensing
        2. 7.3.3.2 Current Regulation
          1. 7.3.3.2.1 Fixed Off-Time Current Chopping
          2. 7.3.3.2.2 Cycle-By-Cycle Current Chopping
      4. 7.3.4 Protection Circuits
        1. 7.3.4.1 VM Supply Undervoltage Lockout (UVLO)
        2. 7.3.4.2 VCP Charge Pump Undervoltage Lockout (CPUV)
        3. 7.3.4.3 OUTx Overcurrent Protection (OCP)
        4. 7.3.4.4 Thermal Shutdown (TSD)
        5. 7.3.4.5 Fault Condition Summary
      5. 7.3.5 Pin Diagrams
        1. 7.3.5.1 Logic-Level Inputs
        2. 7.3.5.2 Tri-Level Inputs
        3. 7.3.5.3 Quad-Level Inputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Low-Power Sleep Mode
      3. 7.4.3 Fault Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Primary Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Current Sense and Regulation
          2. 8.2.1.2.2 Power Dissipation and Output Current Capability
          3. 8.2.1.2.3 Thermal Performance
            1. 8.2.1.2.3.1 Steady-State Thermal Performance
            2. 8.2.1.2.3.2 Transient Thermal Performance
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Alternative Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Current Sense and Regulation
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 HTSSOP Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3.2.2 Cycle-By-Cycle Current Chopping

In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on the EN/IN1 or PH/IN2 pins. This allows for additional control of the current chopping scheme by the external controller. This is shown in Figure 13. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered.

DRV8874 drv887x-cbc.gifFigure 13. Cycle-By-Cycle Current Regulation

In cycle-by-cycle mode, the device will also indicate whenever the H-bridge enters internal current chopping by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This is shown in Figure 14. nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset.

DRV8874 drv887x-nFAULT-chop.gifFigure 14. Cycle-By-Cycle Current Regulation Where nFAULT Acts as Current Chopping Indicator

No device functionality is affected when the nFAULT pin is pulled low for the current chopping indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault (outlined in the Protection Circuits section) from the current chopping indicator, the nFAULT pin can be compared with the control inputs. The current chopping indicator can only assert when the control inputs are commanding a forward or reverse drive state (Figure 10). If the nFAULT pin behavior deviates from the operation shown in Figure 14 then one of the following situations has occurred:

  • If a device fault has occurred, then the nFAULT pin pulls low to indicate a fault condition rather than current chopping. Depending on the device fault, nFAULT may remain low even when the control inputs are commanding the high-Z or slow-decay states.
  • When the control inputs transition from drive to slow decay, the nFAULT pin will go high for tBLKthen be pulled low again if IOUT > ITRIP. This may be caused by a PWM frequency or duty cycle on the control inputs with a off-time that is too short for the IOUT current to decay below the ITRIP threshold. Figure 15 shows an example of this condition. The condition IOUT > ITRIP can be viewed on an oscilloscope as VIPROPI > VREF.
DRV8874 slvsds7-nfault-ipropi-vref.png
Chan. 1 = EN Chan. 2 = nFAULT
Chan. 3 = VREF Chan. 4 = IPROPI
Figure 15. nFAULT Pin When VIPROPI > VVREF with PH/EN Mode and PWM Signal on EN Pin