SLVSDS7B August   2019  – November 2019 DRV8876

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Control Modes
        1. 7.3.2.1 PH/EN Control Mode (PMODE = Logic Low)
        2. 7.3.2.2 PWM Control Mode (PMODE = Logic High)
        3. 7.3.2.3 Independent Half-Bridge Control Mode (PMODE = Hi-Z)
      3. 7.3.3 Current Sense and Regulation
        1. 7.3.3.1 Current Sensing
        2. 7.3.3.2 Current Regulation
          1. 7.3.3.2.1 Fixed Off-Time Current Chopping
          2. 7.3.3.2.2 Cycle-By-Cycle Current Chopping
      4. 7.3.4 Protection Circuits
        1. 7.3.4.1 VM Supply Undervoltage Lockout (UVLO)
        2. 7.3.4.2 VCP Charge Pump Undervoltage Lockout (CPUV)
        3. 7.3.4.3 OUTx Overcurrent Protection (OCP)
        4. 7.3.4.4 Thermal Shutdown (TSD)
        5. 7.3.4.5 Fault Condition Summary
      5. 7.3.5 Pin Diagrams
        1. 7.3.5.1 Logic-Level Inputs
        2. 7.3.5.2 Tri-Level Inputs
        3. 7.3.5.3 Quad-Level Inputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Low-Power Sleep Mode
      3. 7.4.3 Fault Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Primary Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Current Sense and Regulation
          2. 8.2.1.2.2 Power Dissipation and Output Current Capability
          3. 8.2.1.2.3 Thermal Performance
            1. 8.2.1.2.3.1 Steady-State Thermal Performance
            2. 8.2.1.2.3.2 Transient Thermal Performance
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Alternative Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Current Sense and Regulation
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 HTSSOP Layout Example
      2. 10.2.2 VQFN Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
  • PWP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

4.5 V ≤ VVM ≤ 37 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VCP, VM)
IVMQ VM sleep mode current VVM = 24 V, nSLEEP = 0 V, TJ = 25°C 0.75 1 µA
nSLEEP = 0 V 5 µA
IVM VM active mode current VVM = 24 V, nSLEEP = 5 V,
EN/IN1 = PH/IN2 = 0 V		 3 7 mA
tWAKE Turnon time VVM > VUVLO, nSLEEP = 5 V to active 1 ms
tSLEEP Turnoff time nSLEEP = 0 V to sleep mode 1 ms
VVCP Charge pump regulator voltage VCP with respect to VM, VVM = 24 V 5 V
fVCP Charge pump switching frequency 400 kHz
LOGIC-LEVEL INPUTS (EN/IN1, PH/IN2, nSLEEP)
VIL Input logic low voltage VVM < 5 V 0 0.7 V
VVM ≥ 5 V 0 0.8
VIH Input logic high voltage 1.5 5.5 V
VHYS Input hysteresis 200 mV
nSLEEP 50 mV
IIL Input logic low current VI = 0 V –5 5 µA
IIH Input logic high current VI = 5 V 50 75 µA
RPD Input pulldown resistance To GND 100 kΩ
TRI-LEVEL INPUTS (PMODE)
VTIL Tri-level input logic low voltage 0 0.65 V
VTIZ Tri-level input Hi-Z voltage 0.9 1.1 1.2 V
VTIH Tri-level input logic high voltage 1.5 5.5 V
ITIL Tri-level input logic low current VI = 0 V –50 –32 µA
ITIZ Tri-level input Hi-Z current VI = 1.1 V –5 5 µA
ITIH Tri-level input logic high current VI = 5 V 113 150 µA
RTPD Tri-level pulldown resistance To GND 44 kΩ
RTPU Tri-level pullup resistance To internal 5 V 156 kΩ
QUAD-LEVEL INPUTS (IMODE)
VQI2 Quad-level input level 1 Voltage to set quad-level 1 0 0.45 V
RQI2 Quad-level input level 2 Resistance to GND to set quad-level 2 18.6 20 21.4 kΩ
RQI3 Quad-level input level 3 Resistance to GND to set quad-level 3 57.6 62 66.4 kΩ
VQI4 Quad-level input level 4 Voltage to set quad-level 4 2.5 5.5 V
RQPD Quad-level pulldown resistance To GND 136 kΩ
RQPU Quad-level pullup resistance To internal 5 V 68 kΩ
OPEN-DRAIN OUTPUTS (nFAULT)
VOL Output logic low voltage IOD = 5 mA 0.3 V
IOZ Output logic high current VOD = 5 V –2 2 µA
DRIVER OUTPUTS (OUT1, OUT2)
RDS(on)_HS High-side MOSFET on resistance VVM = 24 V, IO = 1 A, TJ = 25°C 350 420 mΩ
RDS(on)_LS Low-side MOSFET on resistance VVM = 24 V, IO = –1 A, TJ = 25°C 350 420 mΩ
VSD Body diode forward voltage ISD = 1 A 0.9 V
tRISE Output rise time VVM = 24 V, OUTx rising 10% to 90% 150 ns
tFALL Output fall time VVM = 24 V, OUTx falling 90% to 10% 150 ns
tPD Input to output propagation delay EN/IN1, PH/IN2 to OUTx, 200 Ω from OUTx to GND 650 ns
tDEAD Output dead time Body diode conducting 300 ns
CURRENT SENSE AND REGULATION (IPROPI, VREF)
AIPROPI Current mirror scaling factor 1000 µA/A
AERR(1) Current mirror scaling error IOUT < 0.15 A,
5.5 V ≤ VVM ≤ 37 V 		 –7.5 7.5 mA
0.15 A ≤ IOUT < 0.5 A,
5.5 V ≤ VVM ≤ 37 V 		 –5 5 %
0.5 A ≤ IOUT ≤ 2 A, 5.5 V ≤ VVM ≤ 37 V,
PWP, –40℃ ≤ TJ < 125℃		 –4 4
0.5 A ≤ IOUT ≤ 2 A, 5.5 V ≤ VVM ≤ 37 V,
PWP, 125℃ ≤ TJ ≤ 150℃		 –5 5
0.5 A ≤ IOUT ≤ 2 A, 5.5 V ≤ VVM ≤ 37 V, RGT –6.5 6.5
tOFF Current regulation off time 25 µs
tDELAY Current sense delay time 1.6 µs
tDEG Current regulation deglitch time 0.6 µs
tBLK Current regulation blanking time 1.1 µs
PROTECTION CIRCUITS
VUVLO Supply undervoltage lockout (UVLO) VVM rising 4.3 4.45 4.6 V
VVM falling 4.2 4.35 4.5 V
VUVLO_HYS Supply UVLO hysteresis 100 mV
tUVLO Supply undervoltage deglitch time 10 µs
VCPUV Charge pump undervoltage lockout VCP with respect to VM, VVCP falling 2.25 V
IOCP Overcurrent protection trip point 3.5 5.5 A
tOCP Overcurrent protection deglitch time 3 µs
tRETRY Overcurrent protection retry time 2 ms
TTSD Thermal shutdown temperature 160 175 190 °C
THYS Thermal shutdown hysteresis 20 °C
(1) At low currents, the IPROPI output has a fixed offset error with respect to the IOUT current through the low-side power MOSFETs.
DRV8876 drv887x-ipropi-timing.gifFigure 1. Timing Parameter Diagram