SLVSFE6A
August 2019 – April 2021
DRV8876N
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
External Components
7.3.2
Control Modes
7.3.2.1
PH/EN Control Mode (PMODE = Logic Low)
7.3.2.2
PWM Control Mode (PMODE = Logic High)
7.3.2.3
Independent Half-Bridge Control Mode (PMODE = Hi-Z)
7.3.3
Protection Circuits
7.3.3.1
VM Supply Undervoltage Lockout (UVLO)
7.3.3.2
VCP Charge Pump Undervoltage Lockout (CPUV)
7.3.3.3
OUTx Overcurrent Protection (OCP)
7.3.3.4
Thermal Shutdown (TSD)
7.3.3.5
Fault Condition Summary
7.3.4
Pin Diagrams
7.3.4.1
Logic-Level Inputs
7.3.4.2
Tri-Level Inputs
7.3.4.3
Quad-Level Inputs
7.4
Device Functional Modes
7.4.1
Active Mode
7.4.2
Low-Power Sleep Mode
7.4.3
Fault Mode
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Primary Application
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Power Dissipation and Output Current Capability
8.2.1.2.2
Thermal Performance
8.2.1.2.2.1
Steady-State Thermal Performance
8.2.1.2.2.2
Transient Thermal Performance
8.2.1.3
Application Curves
8.2.2
Alternative Application
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.3
Application Curves
9
Power Supply Recommendations
9.1
Bulk Capacitance
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
10.2.1
HTSSOP Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Community Resources
11.4
Trademarks
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PWP|16
MPDS371A
Thermal pad, mechanical data (Package|Pins)
PWP|16
PPTD023AC
Orderable Information
slvsfe6a_oa
slvsfe6a_pm
10.2
Layout Example