SLVSD18C June 2015 – August 2017 DRV8880
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The DRV8880 internal logic, indexer, and charge pump are operating unless the nSLEEP pin is brought logic low. In sleep mode the charge pump is disabled, the H-bridge FETs are disabled Hi-Z, and the V3P3 regulator is disabled. tSLEEP must elapse after a falling edge on the nSLEEP pin before the device is in sleep mode. The DRV8880 is brought out of sleep mode automatically if nSLEEP is brought logic high. tWAKE must elapse before the outputs change state after wake-up.
If the ENABLE pin is brought logic low, the H-bridge outputs are disabled, but the charge pump and internal logic will remian active. A rising edge on STEP will advance the indexer, but the outputs will not change state until ENABLE brought logic high.
When VM falls below the VM undervoltage lockout threshold VUVLO2, the output driver and charge pump are disabled, but the internal logic and V3P3 remain active. In this mode, STEP inputs will advance the indexer, but the outputs will remain disabled. If VM falls below the logic undervoltage threshold VUVLO1, the internal logic is reset and the indexer will lose position.
CONDITION | H-BRIDGE | CHARGE PUMP | INDEXER | V3P3 | |
---|---|---|---|---|---|
Operating | 6.5 V < VM < 45 V
nSLEEP pin = 1 ENABLE pin = 1 |
Operating | Operating | Operating | Operating |
Disabled | 6.5 V < VM < 45 V
nSLEEP pin = 1 ENABLE pin = 0 |
Disabled | Operating | Operating | Operating |
Sleep mode | 5.0 V < VM < 45 V
nSLEEP pin = 0 |
Disabled | Disabled | Disabled | Disabled |
Fault encountered | VM undervoltage (UVLO2) | Disabled | Disabled | Operating | Operating |
Logic undervoltage (UVLO1) | Disabled | Disabled | Disabled | Operating | |
VCP undervoltage (CPUV) | Disabled | Operating | Operating | Operating | |
Thermal shutdown (TSD) | Disabled | Operating | Operating | Operating | |
Overcurrent (OCP) | Disabled | Operating | Operating | Operating |