SLVSD18C June   2015  – August 2017 DRV8880

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified System Diagram
      2.      Microstepping Current Waveform
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Indexer Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 RMS Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2  PWM Motor Drivers
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Current Regulation
      5. 7.3.5  Decay Modes
        1. 7.3.5.1 Mode 1: Slow Decay for Increasing and Decreasing Current
        2. 7.3.5.2 Mode 2: Slow Decay for Increasing Current, Mixed Decay for Decreasing current
        3. 7.3.5.3 Mode 3: Mixed Decay for Increasing and Decreasing Current
        4. 7.3.5.4 Mode 4: Slow Decay for Increasing Current, Fast Decay for Decreasing current
        5. 7.3.5.5 Mode 5: Fast Decay for Increasing and Decreasing Current
      6. 7.3.6  Smart Tune
      7. 7.3.7  Adaptive Blanking Time
      8. 7.3.8  Charge Pump
      9. 7.3.9  LDO Voltage Regulator
      10. 7.3.10 Logic and Tri-Level Pin Diagrams
      11. 7.3.11 Power Supplies and Input Pins
      12. 7.3.12 Protection Circuits
      13. 7.3.13 VM UVLO (UVLO2)
      14. 7.3.14 Logic Undervoltage (UVLO1)
      15. 7.3.15 VCP Undervoltage Lockout (CPUV)
      16. 7.3.16 Thermal Shutdown (TSD)
      17. 7.3.17 Overcurrent Protection (OCP)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
        4. 8.2.2.4 Sense Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHR|28
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, V3P3)
VM VM operating voltage 6.5 45 V
IVM VM operating supply current nSLEEP high; ENABLE high; no motor load; VM = 24 V 8 18 mA
IVMQ VM sleep mode supply current nSLEEP low; VM = 24 V; TA = 25°C 28 μA
nSLEEP low; VM = 24 V; TA = 125°C (1) 77
tSLEEP Sleep time nSLEEP low to sleep mode 100 μs
tWAKE Wake-up time nSLEEP high to output transition 1.5 ms
tON Turn-on time VM > VUVLO2 to output transition 1.5 ms
V3P3 LDO regulator voltage External load 0 to 10 mA 2.9 3.3 3.6 V
CHARGE PUMP (VCP, CPH, CPL)
VCP VCP operating voltage VM > 12 V VM + 11.5 V
VUVLO2 < VM < 12 V 2×VM – 1.5
ƒVCP(1) Charge pump switching frequency VM > VUVLO2 175 715 kHz
LOGIC-LEVEL INPUTS (STEP, DIR, ENABLE, nSLEEP, TRQ0, TRQ1, ATE)
VIL Input logic low voltage 0 0.6 V
VIH Input logic high voltage 1.6 5.3 V
VHYS Input logic hysteresis 100 mV
IIL Input logic low current VIN = 0 V –1 1 μA
IIH Input logic high current VIN = 5.0 V 50 100 μA
RPD Pulldown resistance Measured between the pin and GND 100 kΩ
tPD Propagation delay STEP input to current change 450 ns
TRI-LEVEL INPUTS (M0, M1, DECAY0, DECAY1, TOFF)
VIL Tri-level input logic low voltage 0 0.6 V
VIZ Tri-level input Hi-Z voltage 1.1 V
VIH Tri-level input logic high voltage 1.6 5.3 V
VHYS Tri-level input hysteresis 100 mV
IIL Tri-level input logic low current VIN = 0 V –55 –35 μA
IIZ Tri-level input Hi-Z current VIN = 1.3 V 15 μA
IIH Tri-level input logic high current VIN = 3.3 V 85 μA
RPD Tri-level pulldown resistance Measured between the pin and GND 40 kΩ
RPU Tri-level pullup resistance Measured between V3P3 and the pin 45 kΩ
CONTROL OUTPUTS (nFAULT)
VOL Output logic low voltage IO = 4 mA 0.5 V
IOH Output logic high leakage External pullup resistor to 3.3 V –1 1 μA
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
RDS(ON) High-side FET on resistance VM = 24 V, I = 1 A, TA = 25°C 330 mΩ
VM = 24 V, I = 1 A, TA = 125°C (1) 400 440
VM = 6.5 V, I = 1 A, TA = 25°C 430
VM = 6.5 V, I = 1 A, TA = 125°C (1) 500 560
RDS(ON) Low-side FET on resistance VM = 24 V, I = 1 A, TA = 25°C 300 mΩ
VM = 24 V, I = 1 A, TA = 125°C (1) 370 400
VM = 6.5 V, I = 1 A, TA = 25°C 370
VM = 6.5 V, I = 1 A, TA = 125°C (1) 450 490
tRISE Output rise time VM = 24 V, 50 Ω load from xOUTx to GND 70 ns
tFALL Output fall time VM = 24 V, 50 Ω load from VM to xOUTx 70 ns
tDEAD Output dead time (2) 200 ns
Vd Body diode forward voltage IOUT = 0.5 A 0.7 1 V
PWM CURRENT CONTROL (VREF, AISEN, BISEN)
VTRIP xISENSE trip voltage, full scale TRQ at 100%, VREF = 3.3 V 500 mV
TRQ at 75%, VREF = 3.3 V 375
TRQ at 50%, VREF = 3.3 V 250
TRQ at 25%, VREF = 3.3 V 125
AV Amplifier attenuation TRQ at 100% (TRQ0 = 0, TRQ1 = 0) 6.25 6.58 6.91 V/V
TRQ at 75% (TRQ0 = 1, TRQ1 = 0) 6.2 6.56 6.92
TRQ at 50% (TRQ0 = 0, TRQ1 = 1) 6.09 6.51 6.94
TRQ at 25% (TRQ0 = 1, TRQ1 = 1) 5.83 6.38 6.93
tOFF PWM off-time TOFF Logic Low 20 μs
TOFF Logic High 30
TOFF Hi-Z 10
tBLANK PWM blanking time See Table 9 for details 1.8 µs
1.5
1.2
0.9
PROTECTION CIRCUITS
VUVLO2 VM undervoltage lockout VM falling; UVLO2 report 5.8 6.4 V
VM rising; UVLO2 recovery 6.1 6.5
VUVLO1 Logic undervoltage VM falling; logic disabled 4.5 4.9 V
VM rising; logic enabled 4.8 5
VUVLO,HYS undervoltage hysteresis Rising to falling threshold 100 mV
VCPUV Charge pump undervoltage VCP falling; CPUV report VM + 1.8 V
VCP rising; CPUV recovery VM + 1.9
VCPUV,HYS CP undervoltage hysteresis Rising to falling threshold 50 mV
IOCP Overcurrent protection trip level Current through any FET 2.5 3.6 A
VOCP Sense pin overcurrent trip level Voltage at AISEN or BISEN 0.9 1.25 V
tOCP Overcurrent deglitch time 2 μs
tRETRY Overcurrent retry time 0.5 2 ms
TTSD(2) Thermal shutdown temperature Die temperature TJ 150 °C
THYS(2) Thermal shutdown hysteresis Die temperature TJ 35 °C
(1) Specified by design and characterization data
(2) Specified by design and characterization data