SLVSD18C June 2015 – August 2017 DRV8880
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The diagram below gives the input structure for logic-level pins STEP, DIR, ENABLE, nSLEEP, TRQ0, TRQ1, and ATE:
Tri-level logic pins TOFF, M0, M1, DECAY0, and DECAY1 have the following structure: