SLVSD18C June 2015 – August 2017 DRV8880
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
PIN | TYPE | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | PWP | RHR | |||
CPL | 1 | 27 | PWR | Charge pump switching pins | Connect a VM rated, 0.1-µF ceramic capacitor between CPH and CPL |
CPH | 2 | 28 | |||
VCP | 3 | 1 | O | Charge pump output | Connect a 16 V, 0.47 µF ceramic capacitor to VM |
VM | 4, 11 | 2, 9 | PWR | Power supply | Connect to motor supply voltage; bypass to GND with two 0.1 µF (for each pin) plus one bulk capacitor rated for VM |
AOUT1 | 5 | 3 | O | Winding A output | H-bridge outputs, drives one winding of a stepper motor |
AOUT2 | 7 | 5 | |||
AISEN | 6 | 4 | O | Winding A sense | Requires sense resistor to GND; value sets peak current in winding A |
BOUT2 | 8 | 6 | O | Winding B output | H-bridge outputs, drives one winding of a stepper motor |
BOUT1 | 10 | 8 | |||
BISEN | 9 | 7 | O | Winding B sense | Requires sense resistor to GND; value sets peak current in winding B |
GND | 12, 28 | 10, 26 | PWR | Device ground | Must be connected to ground |
ATE | 13 | 11 | I | Smart tune enable pin | Logic high enables smart tune operation; when logic low, the decay mode is set through the DECAYx pins; smart tune must be pulled high prior to power-up or coming out of sleep, or else tied to V3P3 in order to enable smart tune; internal pulldown; see Smart Tune |
VREF | 14 | 12 | I | Full scale current reference input | Voltage on this pin sets the full scale chopping current. |
V3P3 | 15 | 13 | PWR | Internal regulator | Internal supply voltage; bypass to GND with a 6.3 V, 0.47 µF ceramic capacitor; up to 10 mA external load |
TOFF | 16 | 14 | I | Decay mode off time set | Sets the off-time during current chopping; tri-level pin |
nSLEEP | 17 | 15 | I | Sleep mode input | Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown |
nFAULT | 18 | 16 | O | Fault indication pin | Pulled logic low with fault condition; open-drain output requires an external pullup |
DECAY1 | 19 | 17 | I | Decay mode setting pins | Sets the decay mode; see description section; tri-level pin |
DECAY0 | 20 | 18 | |||
ENABLE | 21 | 19 | I | Enable driver input | Logic high to enable device outputs and internal indexer; logic low to disable; internal pulldown |
DIR | 22 | 20 | I | Direction input | Logic level sets the direction of stepping; internal pulldown |
STEP | 23 | 21 | I | Step input | A rising edge causes the indexer to advance one step; internal pulldown |
M1 | 24 | 22 | I | Microstepping mode setting pins | Sets the step mode; full, 1/2, 1/4, 1/8, 1/16; tri-level pin |
M0 | 25 | 23 | |||
TRQ1 | 26 | 24 | I | Torque DAC current scalar | Scales the current by 100%, 75%, 50%, or 25%; internal pulldown |
TRQ0 | 27 | 25 | |||
PAD | PAD | PAD | PWR | Thermal pad | Must be connected to ground |