SLVSEC9C September 2019 – February 2020 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLIES (VDD, VM) | ||||||
IVMQ | VM sleep mode current | VVM = 13.5 V, nSLEEP = 0, TA = 25 °C | 0.35 | 1 | µA | |
VVM = 13.5 V, nSLEEP = 0, TA = 125 °C | 2 | µA | ||||
IVDDQ | VDD sleep mode current | VVM = 13.5 V, VVDD = 3.3 V, nSLEEP = 0, TA = 25 °C | 0.01 | 0.3 | µA | |
VVM = 13.5 V, VVDD = 3.3 V, nSLEEP = 0, TA = 125 °C | 2 | µA | ||||
IVMS | VM standby mode current | VVM = 13.5 V, nSLEEP = 1, Driver = 'OFF', TA = 25 °C | 0.2 | 0.5 | mA | |
VVM = 13.5 V, nSLEEP = 1, Driver = 'OFF', TA = 125 °C | 0.5 | mA | ||||
IVDDS | VDD standby mode current | VVM = 13.5 V, VVDD = 3.3 V, nSLEEP = 1, SPI = 'OFF', TA = 25 °C | 0.6 | 1 | mA | |
VVM = 13.5 V, VVDD = 3.3 V, nSLEEP = 1, SPI = 'OFF', TA = 125 °C | 1 | mA | ||||
IVM | VM operating mode current | VVM = 13.5 V, nSLEEP = 1, All High-Side FETs = 'ON', TA = 25 °C | 2.6 | 5 | mA | |
VVM = 13.5 V, nSLEEP = 1, All High-Side FETs = 'ON', TA = 125 °C | 5 | mA | ||||
IVDD | VDD operating mode current | VVM = 13.5 V, VVDD = 3.3 V, nSLEEP = 1, All High-Side FETs = 'ON', SPI = 'ON' (5 MHz), TA = 25 °C | 2.8 | 5 | mA | |
VVM = 13.5 V, VVDD = 3.3 V, nSLEEP = 1, All High-Side FETs = 'ON', SPI = 'ON' (5 MHz), TA = 125 °C | 5 | mA | ||||
tWAKE | Wake-up time | nSLEEP high to SPI ready | 200 | µs | ||
tSLEEP | Turnoff time | nSLEEP low to device sleep | 20 | µs | ||
LOGIC-LEVEL INPUTS (nSLEEP, SCLK, SDI) | ||||||
VIL | Input logic low voltage | 0 | 0.3*VDD | V | ||
VIH | Input logic high voltage | 0.7*VDD | VDD | V | ||
VHYS | Input logic hysteresis | 200 | mV | |||
IIL | Input logic low current | VIN = 0 V | –1 | 1 | µA | |
IIH | Input logic high current | VIN = VVDD | 34 | 75 | µA | |
CID | Input capacitance | 15 | pF | |||
LOGIC-LEVEL INPUTS (nSCS) | ||||||
VIL | Input logic low voltage | 0 | 0.3*VDD | V | ||
VIH | Input logic high voltage | 0.7*VDD | VDD | V | ||
VHYS | Input logic hysteresis | 200 | mV | |||
IIL | Input logic low current | VIN = 0 V | 34 | 75 | µA | |
IIH | Input logic high current | VIN = VVDD | –1 | 1 | µA | |
CID | Input capacitance | 15 | pF | |||
OPEN-DRAIN OUTPUTS (nFAULT) | ||||||
VOL | Output logic low voltage | IOD = 5 mA | 0 | 0.4 | V | |
IOH | Output logic high current | VOD = 5 V | –1 | 1 | µA | |
COD | Output capacitance | 15 | pF | |||
PUSH-PULL OUTPUTS (SDO) | ||||||
VOL | Output logic low voltage | IOP = 5 mA | 0 | 0.4 | V | |
VOH | Output logic high voltage | IOP = 5 mA | VDD–0.6 | VDD | V | |
IOL | Output logic low current | VOP = 0 V | –1 | 1 | µA | |
IOH | Output logic high current | VOP = VVDD | –1 | 1 | µA | |
COD | Output capacitance | 30 | pF | |||
DRIVER OUTPUTS (OUTx) | ||||||
RDS(ON) | High-side MOSFET on resistance | VVM = 13.5 V, IOUT = 0.5 A, TA = 25°C | 0.75 | 1.1 | Ω | |
VVM = 13.5 V, IOUT = 0.5 A, TA = 125°C | 1.5 | Ω | ||||
Low-side MOSFET on resistance | VVM = 13.5 V, IOUT = 0.5 A, TA = 25°C | 0.75 | 1.1 | Ω | ||
VVM = 13.5 V, IOUT = 0.5 A, TA = 125°C | 1.5 | Ω | ||||
SR | Output rise and fall time (high-side and low-side) | VVM = 13.5 V, 10-90%, RLOAD = 27 Ω, HBx_SR = 0b | 0.6 | V/µs | ||
VVM = 13.5 V, 10-90%, RLOAD = 27 Ω, HBx_SR = 1b | 2.5 | V/µs | ||||
tDEAD | Output dead time (high to low / low to high) | VVM = 13.5 V, SR = 0, HS/LS driver OFF to LS/HS driver ON | 8 | 20 | 32 | µs |
VVM = 13.5 V, SR = 1, HS/LS driver OFF to LS/HS driver ON | 2 | 5 | 15 | µs | ||
tPD | Propagation delay (high-side / low-side ON/OFF) | High-side ON or low-side ON command (SPI last transition) to OUTx transition from Hi-Z state, SR = 0 | 5 | 12 | 25 | µs |
High-side ON or low-side ON command (SPI last transition) to OUTx transition from Hi-Z state, SR = 1 | 3 | 5 | 10 | µs | ||
ILEAK | Leakage current low-side | VOUTx = 13.5 V, nSLEEP = 1, SR = 0b | 6 | 10 | µA | |
VOUTx = 13.5 V, nSLEEP = 1, SR = 1b | 20 | 35 | µA | |||
VOUTx = 13.5 V, nSLEEP = 0 | 4 | 15 | µA | |||
Leakage current high-side | VOUTx = 0 V, nSLEEP = 1 | 2 | µA | |||
VOUTx = 0 V, nSLEEP = 0 | 2 | µA | ||||
PWM MODE | ||||||
fPWM | PWM switching frequency | PWM_CHx_FREQ = 00b | 56 | 80 | 104 | Hz |
PWM_CHx_FREQ = 01b | 70 | 100 | 130 | Hz | ||
PWM_CHx_FREQ = 10b | 140 | 200 | 260 | Hz | ||
PWM_CHx_FREQ = 11b | 1400 | 2000 | 2600 | Hz | ||
PROTECTION CIRCUITS | ||||||
VUVLO | Supply undervoltage lockout (UVLO) | Supply rising | 4.0 | 4.5 | V | |
Supply falling | 3.8 | 4.3 | V | |||
VUVLO_HYS | Supply undervoltage lockout hysteresis | Rising to falling theshold | 200 | mV | ||
tUVLO | Supply undervoltage deglitch time | 10 | µs | |||
VOVP | Supply overvoltage protection (OVP) | Supply rising, EXT_OVP = 0b | 21 | 25 | V | |
Supply falling, EXT_OVP = 0b | 20 | 24 | V | |||
Supply rising, EXT_OVP = 1b | 32.7 | 35 | V | |||
Supply falling, EXT_OVP = 1b | 32 | 34.3 | V | |||
VOVP_HYS | Supply overvoltage protection hysteresis | Rising to falling theshold, EXT_OVP = 0b | 1 | V | ||
Rising to falling theshold, EXT_OVP = 1b | 0.7 | V | ||||
tOVP | Supply overvoltage deglitch time | 10 | µs | |||
VPOR | Logic undervoltage (POR) | Supply rising | 2.45 | 3 | V | |
Supply falling | 2.4 | 2.95 | V | |||
VPOR_HYS | Logic undervoltage hysteresis | Rising to falling theshold | 75 | mV | ||
IOCP | Overcurrent protection trip point(1)(2) | 1.3 | 1.8 | 2.3 | A | |
tOCP | Overcurrent protection deglitch time | OCP_DEG = 000b | 6 | 10 | 14 | µs |
OCP_DEG = 001b | 2.6 | 5 | 7.9 | µs | ||
OCP_DEG = 010b | 0.4 | 2.5 | 5.9 | µs | ||
OCP_DEG = 011b | 0.1 | 1 | 3.4 | µs | ||
OCP_DEG = 100b | 38.2 | 60 | 76.6 | µs | ||
OCP_DEG = 101b | 23.1 | 40 | 51.9 | µs | ||
OCP_DEG = 110b | 18.5 | 30 | 41.5 | µs | ||
OCP_DEG = 111b | 8.4 | 20 | 31.6 | µs | ||
IOLD | Open load detection current | Current flowing from VM to OUTx (High-Side = ON) or OUTx to GND (Low-Side = ON) | 2 | 9 | 18 | mA |
IOLD_NEG | Negative open load detection current | Current flowing from OUTx to VM (High-Side = ON) or GND to OUTx (Low-Side = ON) | 2 | 15 | 30 | mA |
IOLD_LOW | Open load detection current in low current OLD mode | Current flowing from VM to OUTx (High-Side = ON) or OUTx to GND (Low-Side = ON) | 0.2 | 0.8 | 2 | mA |
IOL_GND | Passive OLD current | DRV8908/6/4, FETs in Hi-Z state, current from OUTx to GND during OLD trip | 113 | µA | ||
VOL_GND | Passive OLD voltage threshold | DRV8908/6/4, FETs in Hi-Z state, voltage at OUTx during OLD trip for GND-connected load | 3.3 | V | ||
IOL_VM | Passive OLD current | DRV8908/6/4, FETs in Hi-Z state, current from VM to OUTx for OLD trip, HBX_VM_POLD = 0b | 118 | µA | ||
VOL_VM | Passive OLD voltage threshold | DRV8908/6/4, FETs in Hi-Z state, voltage at OUTx during OLD trip for VM-connected load, HBX_VM_POLD = 0b | 1.2 | V | ||
IOL_VM | Passive OLD current | DRV8908/6/4, FETs in Hi-Z state, current from VM to OUTx for OLD trip, HBX_VM_POLD = 1b | 547 | µA | ||
VOL_VM | Passive OLD voltage threshold | DRV8908/6/4, FETs in Hi-Z state, voltage at OUTx during OLD trip for VM connceted load, HBX_VM_POLD = 1b | 1.8 | V | ||
ROL | Passive OLD detect resistance threshold | DRV8908/6/4, FETs in Hi-Z state, Full bridge connection | 5 | 100 | kΩ | |
ROL | Passive OLD detect resistance threshold | DRV8908/6/4, FETs in Hi-Z State, Load connected to GND | 5 | 100 | kΩ | |
ROL | Passive OLD detect resistance threshold | DRV8908/6/4, FETs in Hi-Z State, Load connected to VM, HBX_VM_POLD = 0b | 5 | 400 | kΩ | |
ROL | Passive OLD detect resistance threshold | DRV8908/6/4, FETs in Hi-Z State, Load connected to VM, HBX_VM_POLD = 1b | 5 | 100 | kΩ | |
tOLD | Open load deglitch time | Active OLD (Continuous Mode) | 2 | 3 | 4 | ms |
tOLD | Open load deglitch time | Active OLD (PWM Mode) | 150 | 200 | 300 | µs |
TOTW | Thermal warning temperature | Die temperature (Tj) | 120 | 140 | 170 | °C |
TOTW_HYS | Thermal warning hysteresis | Die temperature (Tj) | 20 | °C | ||
TOTSD | Thermal shutdown temperature | Die temperature (Tj) | 150 | 175 | 200 | °C |
TOTSD_HYS | Thermal shutdown hysteresis | Die temperature (Tj) | 20 | °C |