SLVSEC9C September 2019 – February 2020 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1
PRODUCTION DATA.
The DRV89xx-Q1 is a pin-to-pin compatible family of integrated multi-channel half-bridge drivers with 4 to 12 half-bridges. The device family features low on-state resistance (RDS(ON)) for improved thermal performance during high-current operation.
These devices can drive brushed-DC (BDC) motors or stepper motors in independent, sequential, or parallel mode. The half-bridges are fully controllable to achieve a forward, reverse, coasting and braking operation of motor.
These devices feature standard 16-bit, 5-MHz serial peripheral interface (SPI) with daisy chain capability for complete configuration and detailed diagnostics. Depending on the device, four or eight programmable PWM generators are integrated to allow for current limiting during motor operation or LED dimming control.
The device includes numerous protection and diagnostic features including an nFAULT pin to alert the system when a fault occurs. The device features a low-current open load detection (OLD) mode to detect open-load conditions when the nominal load current is small and a passive OLD mode for offline OLD. The device is also fully-protected from short-circuit, undervoltage, and over-temperature conditions.
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PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DRV8912-Q1 | HTSSOP (24) | 7.80 mm × 4.40 mm |
DRV8910-Q1 | ||
DRV8908-Q1 | ||
DRV8906-Q1 | ||
DRV8904-Q1 |
Changes from B Revision (December 2019) to C Revision
Changes from A Revision (December 2019) to B Revision
Changes from * Revision (September 2019) to A Revision
DEVICE | NUMBER OF HALF-BRIDGES | NUMBER OF PWM GENERATORS | OPEN-LOAD DETECTION SCHEMES | LINK TO REGISTER MAP |
---|---|---|---|---|
DRV8912-Q1 | 12 | 4 | Active OLD, Low-Current Active OLD, Negative-Current Active OLD | Table 17 |
DRV8910-Q1 | 10 | 4 | Table 18 | |
DRV8908-Q1 | 8 | 8 | Passive OLD, Active OLD, Low-Current Active OLD, Negative-Current Active OLD | Table 50 |
DRV8906-Q1 | 6 | 8 | Table 51 | |
DRV8904-Q1 | 4 | 8 | Table 52 |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
GND | 13 | PWR | Device power ground. Connect the GND pin to the system ground. |
GND | 24 | PWR | Device power ground. Connect the GND pin to the system ground. |
GND | 1 | PWR | Device power ground. Connect the GND pin to the system ground. |
nFAULT | 12 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor. |
nSCS | 19 | I | Serial chip select. A logic low on this pin enables serial interface communication. Internal pull-up. |
nSLEEP | 8 | I | Driver enable pin. When this pin is logic low the device goes to a low-power sleep mode. Internal pull-down. |
OUT1 | 2 | O | Half-bridge 1 output |
OUT2 | 23 | O | Half-bridge 2 output |
OUT3 | 14 | O | Half-bridge 3 output |
OUT4 | 11 | O | Half-bridge 4 output |
OUT5 | 3 | O | Half-bridge 5 output |
OUT6 | 10 | O | Half-bridge 6 output |
OUT7 | 4 | O | Half-bridge 7 output |
OUT8 | 22 | O | Half-bridge 8 output |
OUT9 | 9 | O | Half-bridge 9 output |
OUT10 | 15 | O | Half-bridge 10 output |
OUT11 | 17 | O | Half-bridge 11 output |
OUT12 | 18 | O | Half-bridge 12 output |
SCLK | 20 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pull-down. |
SDI | 5 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pull-down. |
SDO | 7 | O | Serial data output. Data is shifted out on the rising edge of the SCLK pin. |
VDD | 6 | PWR | Logic power supply input. Connect a X5R or X7R, 0.1-μF, VDD-rated ceramic capacitor and greater than or equal to 1-μF bulk capacitance between the VDD and GND pins. |
VM | 16 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
VM | 21 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
GND | 13 | PWR | Device power ground. Connect the GND pin to the system ground. |
GND | 24 | PWR | Device power ground. Connect the GND pin to the system ground. |
GND | 1 | PWR | Device power ground. Connect the GND pin to the system ground. |
NC | 17 | — | Not connected |
NC | 18 | — | Not connected |
nFAULT | 12 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor. |
nSCS | 19 | I | Serial chip select. A logic low on this pin enables serial interface communication. Internal pull-up. |
nSLEEP | 8 | I | Driver enable pin. When this pin is logic low the device goes to a low-power sleep mode. Internal pull-down. |
OUT1 | 2 | O | Half-bridge 1 output |
OUT2 | 23 | O | Half-bridge 2 output |
OUT3 | 14 | O | Half-bridge 3 output |
OUT4 | 11 | O | Half-bridge 4 output |
OUT5 | 3 | O | Half-bridge 5 output |
OUT6 | 10 | O | Half-bridge 6 output |
OUT7 | 4 | O | Half-bridge 7 output |
OUT8 | 22 | O | Half-bridge 8 output |
OUT9 | 9 | O | Half-bridge 9 output |
OUT10 | 15 | O | Half-bridge 10 output |
SCLK | 20 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pull-down. |
SDI | 5 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pull-down. |
SDO | 7 | O | Serial data output. Data is shifted out on the rising edge of the SCLK pin. |
VDD | 6 | PWR | Logic power supply input. Connect a X5R or X7R, 0.1-μF, VDD-rated ceramic capacitor and greater than or equal to 1-μF bulk capacitance between the VDD and GND pins. |
VM | 16 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
VM | 21 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
GND | 13 | PWR | Device power ground. Connect the GND pin to the system ground. |
GND | 24 | PWR | Device power ground. Connect the GND pin to the system ground. |
GND | 1 | PWR | Device power ground. Connect the GND pin to the system ground. |
NC | 9 | — | Not connected |
NC | 15 | — | Not connected |
NC | 17 | — | Not connected |
NC | 18 | — | Not connected |
nFAULT | 12 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor. |
nSCS | 19 | I | Serial chip select. A logic low on this pin enables serial interface communication. Internal pull-up. |
nSLEEP | 8 | I | Driver enable pin. When this pin is logic low the device goes to a low-power sleep mode. Internal pull-down. |
OUT1 | 2 | O | Half-bridge 1 output |
OUT2 | 23 | O | Half-bridge 2 output |
OUT3 | 14 | O | Half-bridge 3 output |
OUT4 | 11 | O | Half-bridge 4 output |
OUT5 | 3 | O | Half-bridge 5 output |
OUT6 | 10 | O | Half-bridge 6 output |
OUT7 | 4 | O | Half-bridge 7 output |
OUT8 | 22 | O | Half-bridge 8 output |
SCLK | 20 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pull-down. |
SDI | 5 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pull-down. |
SDO | 7 | O | Serial data output. Data is shifted out on the rising edge of the SCLK pin. |
VDD | 6 | PWR | Logic power supply input. Connect a X5R or X7R, 0.1-μF, VDD-rated ceramic capacitor and greater than or equal to 1-μF bulk capacitance between the VDD and GND pins. |
VM | 16 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
VM | 21 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
GND | 13 | PWR | Device power ground. Connect the GND pin to the system ground. |
GND | 24 | PWR | Device power ground. Connect the GND pin to the system ground. |
GND | 1 | PWR | Device power ground. Connect the GND pin to the system ground. |
NC | 4 | — | Not connected |
NC | 9 | — | Not connected |
NC | 15 | — | Not connected |
NC | 17 | — | Not connected |
NC | 18 | — | Not connected |
NC | 22 | — | Not connected |
nFAULT | 12 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor. |
nSCS | 19 | I | Serial chip select. A logic low on this pin enables serial interface communication. Internal pull-up. |
nSLEEP | 8 | I | Driver enable pin. When this pin is logic low the device goes to a low-power sleep mode. Internal pull-down. |
OUT1 | 2 | O | Half-bridge 1 output |
OUT2 | 23 | O | Half-bridge 2 output |
OUT3 | 14 | O | Half-bridge 3 output |
OUT4 | 11 | O | Half-bridge 4 output |
OUT5 | 3 | O | Half-bridge 5 output |
OUT6 | 10 | O | Half-bridge 6 output |
SCLK | 20 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pull-down. |
SDI | 5 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pull-down. |
SDO | 7 | O | Serial data output. Data is shifted out on the rising edge of the SCLK pin. |
VDD | 6 | PWR | Logic power supply input. Connect a X5R or X7R, 0.1-μF, VDD-rated ceramic capacitor and greater than or equal to 1-μF bulk capacitance between the VDD and GND pins. |
VM | 16 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
VM | 21 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
GND | 13 | PWR | Device power ground. Connect the GND pin to the system ground. |
GND | 24 | PWR | Device power ground. Connect the GND pin to the system ground. |
GND | 1 | PWR | Device power ground. Connect the GND pin to the system ground. |
NC | 3 | — | Not connected |
NC | 4 | — | Not connected |
NC | 9 | — | Not connected |
NC | 10 | — | Not connected |
NC | 15 | — | Not connected |
NC | 17 | — | Not connected |
NC | 18 | — | Not connected |
NC | 22 | — | Not connected |
nFAULT | 12 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor. |
nSCS | 19 | I | Serial chip select. A logic low on this pin enables serial interface communication. Internal pull-up. |
nSLEEP | 8 | I | Driver enable pin. When this pin is logic low the device goes to a low-power sleep mode. Internal pull-down. |
OUT1 | 2 | O | Half-bridge 1 output |
OUT2 | 23 | O | Half-bridge 2 output |
OUT3 | 14 | O | Half-bridge 3 output |
OUT4 | 11 | O | Half-bridge 4 output |
SCLK | 20 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pull-down. |
SDI | 5 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pull-down. |
SDO | 7 | O | Serial data output. Data is shifted out on the rising edge of the SCLK pin. |
VDD | 6 | PWR | Logic power supply input. Connect a X5R or X7R, 0.1-μF, VDD-rated ceramic capacitor and greater than or equal to 1-μF bulk capacitance between the VDD and GND pins. |
VM | 16 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
VM | 21 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |