SLVSEC9C September 2019 – February 2020 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1
PRODUCTION DATA.
The PWM Map Control 3 register is shown in Figure 93 and described in Table 38.
Register access type: Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HB12_PWM_MAP | HB11_PWM_MAP | HB10_PWM_MAP | HB9_PWM_MAP | ||||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7-6 | HB12_PWM_MAP | R/W | 00b |
00b = HB12 mapped to PWM channel 1 01b = HB12 mapped to PWM channel 2 10b = HB12 mapped to PWM channel 3 11b = HB12 mapped to PWM channel 4 |
5-4 | HB11_PWM_MAP | R/W | 00b |
00b = HB11 mapped to PWM channel 1 01b = HB11 mapped to PWM channel 2 10b = HB11 mapped to PWM channel 3 11b = HB11 mapped to PWM channel 4 |
3-2 | HB10_PWM_MAP | R/W | 00b |
00b = HB10 mapped to PWM channel 1 01b = HB10 mapped to PWM channel 2 10b = HB10 mapped to PWM channel 3 11b = HB10 mapped to PWM channel 4 |
1-0 | HB9_PWM_MAP | R/W | 00b |
00b = HB9 mapped to PWM channel 1 01b = HB9 mapped to PWM channel 2 10b = HB9 mapped to PWM channel 3 11b = HB9 mapped to PWM channel 4 |