SLOSE62A January   2021  – May 2022 DRV8935

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control and Current Regulation
      2. 7.3.2 Decay Modes
        1. 7.3.2.1 Blanking time
      3. 7.3.3 Charge Pump
      4. 7.3.4 Linear Voltage Regulators
      5. 7.3.5 Logic and Quad-Level Pin Diagrams
      6. 7.3.6 nFAULT Pin
      7. 7.3.7 Protection Circuits
        1. 7.3.7.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.7.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.7.3 Overcurrent Protection (OCP)
        4. 7.3.7.4 Thermal Shutdown (OTSD)
        5. 7.3.7.5 Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Operating Mode (nSLEEP = 1)
      3. 7.4.3 nSLEEP Reset Pulse
      4. 7.4.4 Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Current Regulation
      3. 8.2.3 Power Dissipation Calculation and Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Functions

PINTYPEDESCRIPTION
NAMEPWPRGE
IN12520IPWM input. Logic controls the state of Half-bridge 1; internal pulldown.
IN22419IPWM input. Logic controls the state of Half-bridge 2; internal pulldown.
IN32318IPWM input. Logic controls the state of Half-bridge 3; internal pulldown.
IN42217IPWM input. Logic controls the state of Half-bridge 4; internal pulldown.
OUT14, 53OOutput of Half-bridge 1.
OUT26, 74OOutput of Half-bridge 2.
OUT310, 116OOutput of Half-bridge 3.
OUT48, 95OOutput of Half-bridge 4.
VREF121813IReference voltage input pin. Controls the current level for Half-bridges 1 and 2.
VREF341712IReference voltage input pin. Controls the current level for Half-bridges 3 and 4.
NC20, 2115, 16-No Connect.
CPH2823PWRCharge pump switching node. Connect a X7R, 0.022-μF, VM-rated ceramic capacitor from CPH to CPL.
CPL2722
GND149PWRDevice ground. Connect to system ground.
TOFF1914ISets the off-time during current chopping; quad-level pin.
DVDD1510PWRLogic supply voltage. Connect a X7R, 0.47-μF to 1-μF, 6.3-V or 10-V rated ceramic capacitor to GND.
VCP124OCharge pump output. Connect a X7R, 0.22-μF, 16-V ceramic capacitor to VM.
VM2, 131, 8PWRPower supply. Connect to supply voltage and bypass to PGND with two 0.01-μF ceramic capacitors (one for each pin) plus a bulk capacitor rated for VM.
PGND3, 122, 7PWRCommon power ground pin for all the half-bridges. Connect to system ground.
nFAULT1611OFault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor.
nSLEEP2621ISleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown resistor.
PAD---Thermal pad. Connect to system ground.