SLOSE83 March   2023 DRV8952

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Feature Description
    4. 7.4  Independent Half-bridge Operation
    5. 7.5  Current Sensing and Regulation
      1. 7.5.1 Current Sensing and Feedback
      2. 7.5.2 Current Sensing with External Resistor
      3. 7.5.3 Current Regulation
    6. 7.6  Charge Pump
    7. 7.7  Linear Voltage Regulator
    8. 7.8  VCC Voltage Supply
    9. 7.9  Logic Level Pin Diagram
    10. 7.10 Protection Circuits
      1. 7.10.1 VM Undervoltage Lockout (UVLO)
      2. 7.10.2 VCP Undervoltage Lockout (CPUV)
      3. 7.10.3 Logic Supply Power on Reset (POR)
      4. 7.10.4 Overcurrent Protection (OCP)
      5. 7.10.5 Thermal Shutdown (OTSD)
      6. 7.10.6 nFAULT Output
      7. 7.10.7 Fault Condition Summary
    11. 7.11 Device Functional Modes
      1. 7.11.1 Sleep Mode (nSLEEP = 0)
      2. 7.11.2 Operating Mode
      3. 7.11.3 nSLEEP Reset Pulse
      4. 7.11.4 Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Driving Solenoid Loads
        1. 8.1.1.1 Solenoid Driver Typical Application
        2. 8.1.1.2 Thermal Calculations
          1. 8.1.1.2.1 Power Loss Calculations
          2. 8.1.1.2.2 Junction Temperature Estimation
        3. 8.1.1.3 Application Performance Plots
      2. 8.1.2 Driving Stepper Motors
        1. 8.1.2.1 Stepper Driver Typical Application
        2. 8.1.2.2 Power Loss Calculations
        3. 8.1.2.3 Junction Temperature Estimation
      3. 8.1.3 Driving Brushed-DC Motors
        1. 8.1.3.1 Brushed-DC Driver Typical Application
        2. 8.1.3.2 Power Loss Calculation
        3. 8.1.3.3 Junction Temperature Estimation
        4. 8.1.3.4 Driving Single Brushed-DC Motor
      4. 8.1.4 Driving Thermoelectric Coolers (TEC)
      5. 8.1.5 Driving Brushless DC Motors
  9. 9 Package Thermal Considerations
    1. 9.1 DDW Package
      1. 9.1.1 Thermal Performance
        1. 9.1.1.1 Steady-State Thermal Performance
        2. 9.1.1.2 Transient Thermal Performance
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
    2. 10.2 Power Supplies
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 PCB Material Recommendation
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES (VM, DVDD)
IVMVM operating supply currentnSLEEP = 1, No load, VCC = External 5V

4

7

mA
nSLEEP = 1, No load, VCC = DVDD

6

9

IVMQVM sleep mode supply currentnSLEEP = 0

3

8

μA
tSLEEPSleep timenSLEEP = 0 to sleep-mode120μs
tRESETnSLEEP reset pulsenSLEEP low to clear fault2040μs
tWAKEWake-up timenSLEEP = 1 to output transition0.851.2ms
tONTurn-on timeVM > UVLO to output transition0.851.3ms
VDVDDInternal regulator voltageNo external load, 6 V < VVM < 55 V4.7555.25V
No external load, VVM = 4.5 V

4.2

4.35

V

CHARGE PUMP (VCP, CPH, CPL)
VVCPVCP operating voltage6 V < VVM < 55 VVVM + 5V
f(VCP)Charge pump switching frequencyVVM > UVLO; nSLEEP = 1360kHz
LOGIC-LEVEL INPUTS (IN1, IN2, IN3, IN4, EN1, EN2, EN3, EN4, MODE, OCPM, nSLEEP)
VILInput logic-low voltage00.6V
VIHInput logic-high voltage1.55.5V
VHYSInput logic hysteresis (all pins except nSLEEP)100mV

VHYS_nSLEEP

nSLEEP logic hysteresis

300

mV

IILInput logic-low currentVIN = 0 V–11μA
IIHInput logic-high currentVIN = DVDD50μA

t1

ENx high to OUTx high delay

INx = 1

2

μs

t2

ENx low to OUTx low delayINx = 1

2

μs

t3

ENx high to OUTx low delayINx = 0

2

μs

t4

ENx low to OUTx high delayINx = 0

2

μs

t5

INx high to OUTx high delay

600

ns

t6INx low to OUTx low delay600ns
CONTROL OUTPUTS (nFAULT)
VOLOutput logic-low voltageIO = 5 mA0.35V
IOHOutput logic-high leakage–11μA
MOTOR DRIVER OUTPUTS (OUT1, OUT2, OUT3, OUT4)
RDS(ONH,DDW)High-side FET on resistance, DDW package

TJ = 25 °C, IO = -5 A, DDW Package

54

63

mΩ
TJ = 125 °C, IO = -5 A, DDW Package

80

94

mΩ
TJ = 150 °C, IO = -5 A, DDW Package

90

105mΩ
RDS(ONL,DDW)Low-side FET on resistance, DDW packageTJ = 25 °C, IO = 5 A, DDW Package

58

66

mΩ
TJ = 125 °C, IO = 5 A, DDW Package

85

98

mΩ
TJ = 150 °C, IO = 5 A, DDW Package

94

107mΩ
RDS(ONH,PWP)High-side FET on resistanc, PWP packageTJ = 25 °C, IO = -5 A, PWP Package

58

65

mΩ
TJ = 125 °C, IO = -5 A, PWP Package

85

98

mΩ
TJ = 150 °C, IO = -5 A, PWP Package

94

107

mΩ
RDS(ONL,PWP)Low-side FET on resistance, PWP packageTJ = 25 °C, IO = 5 A, PWP Package

55

66

mΩ
TJ = 125 °C, IO = 5 A, PWP Package

83

100

mΩ
TJ = 150°C, IO = 5 A, PWP Package

94

116

mΩ
tRFOutput rise/fall timeIO = 5 A, MODE = 0 for DDW package or for PWP package, between 10% and 90%

140

ns

IO = 5 A, MODE = 1 for DDW package, between 10% and 90%

70

ns

tD

Output dead time

VM = 24V, IO = 5 A

300

ns

CURRENT SENSE AND REGULATION (IPROPI, VREF)

AIPROPI

Current mirror gain

212

μA/A

KV

Transimpedance Gain

VREF = 3.3 V, PWP Package

0.625

0.66

0.695

V/A

AERR

Current mirror scaling error

10% to 20% rated current

-7

9

%

20% to 40% rated current

-4

6

40% to 100% rated current

-3.5

5

IVREF

VREF Leakage Current

VREF = 3.3 V

20

nA

tOFF

PWM off-time

16

μs

tDEG

Current regulation deglitch time

0.5

μs

tBLK

Current Regulation Blanking time

1.5

μs

tDELAY

Current sense delay time

2

μs
PROTECTION CIRCUITS
VUVLOVM UVLO lockoutVM falling4.14.234.35V
VM rising4.24.354.47
VCCUVLOVCC UVLO lockout

VCC falling

2.7

2.8

2.9

V

VCC rising

2.75

2.92

3.05

VUVLO,HYSUndervoltage hysteresisRising to falling threshold110mV
VCPUVCharge pump undervoltageVCP fallingVVM + 2V
IOCPOvercurrent protectionCurrent through any FET

7.6

A
tOCPOvercurrent detection delay

2.2

μs

tRETRY

Overcurrent retry time

4.1

ms

TOTSDThermal shutdownDie temperature TJ150165180°C
THYS_OTSDThermal shutdown hysteresisDie temperature TJ20°C
Figure 6-1 IPROPI Timing Diagram