SNLS348E October   2011  – January 2015 DS100BR210

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics — Serial Management Bus Interface
    7. 7.7 Timing Requirements — LOS and ENABLE / DISABLE Timing
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
      2. 8.3.2 Typical 4-Level Input Thresholds
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBus Slave Mode
      3. 8.4.3 SMBus Master Mode
      4. 8.4.4 Signal Conditioning Settings
    5. 8.5 Programming
      1. 8.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 8.5.2 Transfer Of Data Via the SMBus
      3. 8.5.3 SMBus Transactions
      4. 8.5.4 Writing a Register
      5. 8.5.5 Reading a Register
      6. 8.5.6 EEPROM Programming
        1. 8.5.6.1 Master EEPROM Programming
        2. 8.5.6.2 EEPROM Address Mapping
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Signal Integrity in 10G-KR Applications
      2. 9.1.2 OOB (Out-of-Band) Functionality in SAS/SATA Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Performance Plots
        1. 9.2.3.1 Equalization Results (Pre-Channel Only)
        2. 9.2.3.2 Equalization and De-Emphasis Results (Pre-channel and Post-channel, No Tx Source De-emphasis)
        3. 9.2.3.3 Equalization and De-Emphasis Results (Pre-channel and Post-channel, -6 dB Tx Source De-emphasis)
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypass
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

  • Absolute Maximum Ratings for Soldering, SNOA549
  • IC Package Thermal Metrics application report, SPRA953
  • EEPROM Programming and Master Mode, SNLA228

12.2 Trademarks

All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.