SNLS348E October   2011  – January 2015 DS100BR210

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics — Serial Management Bus Interface
    7. 7.7 Timing Requirements — LOS and ENABLE / DISABLE Timing
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
      2. 8.3.2 Typical 4-Level Input Thresholds
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBus Slave Mode
      3. 8.4.3 SMBus Master Mode
      4. 8.4.4 Signal Conditioning Settings
    5. 8.5 Programming
      1. 8.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 8.5.2 Transfer Of Data Via the SMBus
      3. 8.5.3 SMBus Transactions
      4. 8.5.4 Writing a Register
      5. 8.5.5 Reading a Register
      6. 8.5.6 EEPROM Programming
        1. 8.5.6.1 Master EEPROM Programming
        2. 8.5.6.2 EEPROM Address Mapping
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Signal Integrity in 10G-KR Applications
      2. 9.1.2 OOB (Out-of-Band) Functionality in SAS/SATA Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Performance Plots
        1. 9.2.3.1 Equalization Results (Pre-Channel Only)
        2. 9.2.3.2 Equalization and De-Emphasis Results (Pre-channel and Post-channel, No Tx Source De-emphasis)
        3. 9.2.3.3 Equalization and De-Emphasis Results (Pre-channel and Post-channel, -6 dB Tx Source De-emphasis)
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypass
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

10.1 3.3-V or 2.5-V Supply Mode Operation

The DS100BR210 has an optional internal voltage regulator to provide the 2.5 V supply to the device. In 3.3 V mode, the VIN pin = 3.3 V is used to supply power to the device and the VDD pins should be left open. The internal regulator will provide the 2.5 V to the VDD pins of the device and a 0.1 μF cap is needed at each of the two VDD pins for power supply de-coupling (total capacitance should be ≤ 0.2 μF). The VDD_SEL pin must be tied to GND to enable the internal regulator. In 2.5 V mode, the VIN pin should be left open and 2.5 V supply must be applied to the VDD pins. The VDD_SEL pin must be left open (no connect) to disable the internal regulator.

The DS100BR210 can be configured for 2.5 V operation or 3.3 V operation. The lists below outline required connections for each supply selection.

    3.3 V Mode of Operation

  • Tie VDD_SEL = GND.
  • Feed 3.3 V supply into VIN pin. Local 10 µF and 1 µF decoupling at VIN is recommended.
  • See information on VDD bypass in Power Supply Bypass.
  • SDA and SCL pins should connect pull-up resistor to VIN.
  • Any 4-Level input which requires a connection to "Logic 1" should use a 1 kΩ resistor to VIN.

    2.5 V Mode of Operation

  • VDD_SEL = Float
  • VIN = Float
  • Feed 2.5 V supply into VDD pins. Local 10 µF and 1 µF decoupling at VIN is recommended.
  • See information on VDD bypass in Power Supply Bypass.
  • SDA and SCL pins connect pull-up resistor to VDD for 2.5 V or 3.3 V microcontroller SMBus IO.
  • Any 4-Level input which requires a connection to "Logic 1" should use a 1 kΩ resistor to VDD.

NOTE

The DAP (bottom solder pad) is the GND connection.
111power.gifFigure 39. 3.3 V or 2.5 V Supply Connection Diagram

10.2 Power Supply Bypass

Two approaches are recommended to ensure that the DS100BR210 is provided with an adequate power supply bypass. First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the printed circuit board. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.1 μF bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to the device. Small body size capacitors (such as 0402) reduce the capacitors' parasitic inductance and also help in placement close to the VDD pin. If possible, the layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance.