SNLS340E November   2011  – November 2015 DS100KR800

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics - Serial Management Bus Interface
    7. 6.7 Timing Requirements - Serial Bus Interface Timing Specifications
    8. 6.8 Typical Characteristics
      1. 6.8.1 Electrical Performance
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Configuration Guidelines
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pin Control Mode
      2. 7.4.2 SMBUS Mode
    5. 7.5 Programming
      1. 7.5.1 SMBUS Master Mode
    6. 7.6 Register Maps
      1. 7.6.1 System Management Bus (SMBus) and Configuration Registers
        1. 7.6.1.1 Transfer of Data Through the SMBus
        2. 7.6.1.2 SMBus Transactions
        3. 7.6.1.3 Writing a Register
        4. 7.6.1.4 Reading a Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 3.3-V or 2.5-V Supply Mode Operation
    2. 9.2 Power Supply Bypassing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

NJY Package
54-Pin WQFN
Top View
DS100KR800 30148092.gif

Pin Functions: Common Connections(1)(2)(3)(4)

PIN TYPE DESCRIPTION
NAME NO.
DIFFERENTIAL HIGH SPEED INPUTS AND OUTPUTS
IN_A_0+, IN_A_0-,
IN_A_1+, IN_A_1-,
IN_A_2+, IN_A_2-,
IN_A_3+, IN_A_3-		 10, 11,
12, 13,
15, 16,
17, 18		 I Inverting and noninverting differential inputs to bank A equalizer. A gated on-chip 50-Ω termination resistor connects INA_n+ to VDD and INA_n- to VDD when enabled. AC coupling required on high-speed I/O.
IN_B_0+, IN_B_0-,
IN_B_1+, IN_B_1-,
IN_B_2+, IN_B_2-,
IN_B_3+, IN_B_3-,		 1, 2,
3, 4,
5, 6,
7, 8		 I Inverting and noninverting differential inputs to bank B equalizer. A gated on-chip 50-Ω termination resistor connects INB_n+ to VDD and INB_n- to VDD when enabled. AC coupling required on high-speed I/O.
OUT_A_0+, OUT_A_0-,
OUT_A_1+, OUT_A_1-,
OUT_A_2+, OUT_A_2-,
OUT_A_3+, OUT_A_3-		 35, 34,
33, 32,
31, 30,
29, 28		 O Inverting and noninverting 50-Ω driver bank A outputs with de-emphasis. Compatible with AC-coupled CML inputs. AC coupling required on high-speed I/O.
OUT_B_0+, OUT_B_0-,
OUT_B_1+, OUT_B_1-,
OUT_B_2+, OUT_B_2-,
OUT_B_3+, OUT_B_3-, 		45, 44,
43, 42,
40, 39,
38, 37		 O Inverting and noninverting 50-Ω driver bank B outputs with de-emphasis. Compatible with AC-coupled CML inputs. AC coupling required on high-speed I/O.
CONTROL PINS — SHARED (LVCMOS)
ENSMB 48 I, LVCMOS System Management Bus (SMBus) enable pin
Tie 1 kΩ to VDD = Register Access SMBus Slave mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1 kΩ to GND = Pin Mode
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
RESET 52 I, LVCMOS LOW = Device is enabled (Normal Operation)
HIGH = Low Power Mode
VDD_SEL 25 I, FLOAT Controls the internal regulator
Float = 2.5-V mode
Tie GND = 3.3-V mode
POWER
GND DAP Power Ground pad (DAP - die attach pad).
VDD 9, 14, 36, 41, 51 Power Power supply pins CML/analog
2.5-V mode, connect to 2.5 V
3.3-V mode, connect 0.1-µF cap to each VDD pin
VIN 24 Power In 3.3-V mode, feed 3.3 V to VIN
In 2.5-V mode, leave floating.
(1) LVCMOS inputs without the Float conditions must be driven to a logic low or high at all times or operation is not ensured.
(2) Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
(3) For 3.3-V mode operation, VIN pin = 3.3 V and the VDD for the 4-level input is 3.3 V.
(4) For 2.5-V mode operation, VDD pin = 2.5 V and the VDD for the 4-level input is 2.5 V.

Pin Functions: SMBus/EEPROM Control

PIN TYPE DESCRIPTION
NAME NO.
ENSMB = 1 (SMBUS MODE)
AD0-AD3 54, 53, 47, 46 I, LVCMOS ENSMB master or slave mode
User set SMBus Slave Address Inputs in SMBus mode.
READ_EN 26 I, 4-LEVEL,
LVCMOS		 When using an external EEPROM, a transition from high to low starts the load from the external EEPROM
SCL 50 I, LVCMOS,
O, OPEN-Drain		 ENSMB master or slave mode
SMBUS clock input pin is enabled.
Clock output when loading EEPROM configuration (master mode).
SDA 49 I, LVCMOS,
O, OPEN-Drain		 ENSMB master or slave mode
The SMBus bidirectional SDA pin is enabled. Data input or open-drain output.
ENSMB = 0 (PIN MODE)
MODE 21 I, 4-LEVEL,
LVCMOS 		Tie 1 kΩ to VDD = 10G-KR mode operation
Tie 1 kΩ to GND = 10G mode operation
SD_TH 26 I, 4-LEVEL,
LVCMOS 		Controls the internal signal detect threshold
See Table 4
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
INPUT_EN 22 I, 4-LEVEL,
LVCMOS 		Tie 1 kΩ to VDD = normal operation
OUTPUTS
ALL_DONE 27 O, LVCMOS Valid register load status output
HIGH = external EEPROM load failed
LOW = external EEPROM load passed

Pin Functions: Pin Control

PIN TYPE DESCRIPTION
NAME NO.
ENSMB = 0 (PIN MODE)
DEMA0, DEMA1, DEMB0, DEMB1 49, 50, 53, 54 I, 4-LEVEL,
LVCMOS 		DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output driver when in Gen1/2 mode. The pins are only active when ENSMB is deasserted (low). The 8 channels are organized into two banks. Bank A is controlled with the DEMA [1:0] pins and bank B is controlled with the DEMB[1:0] pins. When ENSMB is high the SMBus registers provide independent control of each channel. The DEMA[1:0] pins are converted to SMBUS SCL/SDA and DEMB[1:0] pins are converted to AD0, AD1 inputs.
See Table 3
EQA0, EQA1,
EQB0, EQB1		 20, 19, 46, 47 I, 4-LEVEL,
LVCMOS		 EQA[1:0] and EQB[1:0] control the level of equalization on the input pins. The pins are active only when ENSMB is deasserted (low). The 8 channels are organized into two banks. Bank A is controlled with the EQA[1:0] pins and bank B is controlled with the EQB[1:0] pins. When ENSMB is high the SMBus registers provide independent control of each channel. The EQB[1:0] pins are converted to SMBUS AD2/ AD3 inputs.
See Table 2
MODE 21 I, 4-LEVEL,
LVCMOS 		Tie 1 kΩ to VDD = 10G-KR mode operation
Tie 1 kΩ to GND = 10G mode operation
SD_TH 26 I, 4-LEVEL,
LVCMOS 		Controls the internal signal detect threshold
See Table 4
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
INPUT_EN 22 I, 4-LEVEL,
LVCMOS 		Tie 1 kΩ to VDD = normal operation
RESERVED 23 I, FLOAT Float = normal operation