SNLS340E November   2011  – November 2015 DS100KR800

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics - Serial Management Bus Interface
    7. 6.7 Timing Requirements - Serial Bus Interface Timing Specifications
    8. 6.8 Typical Characteristics
      1. 6.8.1 Electrical Performance
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Configuration Guidelines
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pin Control Mode
      2. 7.4.2 SMBUS Mode
    5. 7.5 Programming
      1. 7.5.1 SMBUS Master Mode
    6. 7.6 Register Maps
      1. 7.6.1 System Management Bus (SMBus) and Configuration Registers
        1. 7.6.1.1 Transfer of Data Through the SMBus
        2. 7.6.1.2 SMBus Transactions
        3. 7.6.1.3 Writing a Register
        4. 7.6.1.4 Reading a Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 3.3-V or 2.5-V Supply Mode Operation
    2. 9.2 Power Supply Bypassing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

See (1)
MIN MAX UNIT
Supply voltage (VDD = 2.5-V mode) –0.5 2.75 V
Supply voltage (VIN = 3.3-V mode) –0.5 4 V
LVCMOS input or output voltage –0.5 4 V
CML input voltage –0.5 (VDD + 0.5) V
CML input current –30 30 ma
Junction temperature 125 °C
Lead temperature Soldering (4 sec.)(2) 260 °C
Derate NJY0054A package 52.6 mW/°C
Storage temperature, Tstg –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For soldering specifications: see product folder at SNOA549.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±3000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
Machine model, STD - JESD22-A115-A ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage 2.5-V mode 2.375 2.5 2.625 V
3.3-V mode 3.0 3.3 3.6 V
Ambient temperature –40 25 85 °C
SMBus (SDA, SCL) 3.6 V
Supply noise up to 50 MHz(1) 100 mVp-p
(1) Allowed supply noise (mVp-p sine wave) under typical conditions.

6.4 Thermal Information

THERMAL METRIC(1) DS100KR800 UNIT
NJY (WQFN)
54 PINS
RθJA Junction-to-ambient thermal resistance, No Airflow, 4-layer JEDEC 26.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 10.8 °C/W
RθJB Junction-to-board thermal resistance 4.4 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 4.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

See (3)(2)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
POWER
PD Power dissipation EQ enabled, VOD = 1 Vp-p, INPUT_EN = 1, RESET = 0 VDD = 2.5-V supply 500 700 mW
VIN = 3.3-V supply 660 900 mW
LVCMOS / LVTTL DC SPECIFICATIONS
Vih High level Input voltage 3.3-V mode operation (VIN = 3.3 V) 2 3.6 V
Vil Low level Input voltage 3.3-V mode operation (VIN = 3.3 V) 0 0.8 V
Voh High level output voltage
(ALL_DONE pin)		 Ioh = –4 mA 2 V
Vol Low level output voltage
(ALL_DONE pin)		 Iol = 4 mA 0.4 V
Iih Input high current (RESET pin) VIN = 3.6 V, LVCMOS = 3.6 V –15 15 µA
Input high current
with internal resistors
(4–level input pin)		 VIN = 3.6 V, LVCMOS = 3.6 V 20 150 µA
Iil Input low current (RESET pin) VIN = 3.6 V, LVCMOS = 0 V –15 15 µA
Input low current
with internal resistors
(4–level input pin)		 VIN = 3.6 V, LVCMOS = 0 V –160 –40 µA
CML RECEIVER INPUTS (IN_n+, IN_n-)
RLrx-diff RX package pins plus Si differential return loss 0.05 GHz - 7.5 GHz –15 dB
7.5 GHz - 15 GHz –5 dB
RLrx-cm Common-mode RX return loss 0.05 GHz - 5 GHz –10 dB
Zrx-dc RX DC common-mode impedance Tested at VDD = 0 40 50 60 Ω
Zrx-diff-dc RX DC differential mode impedance Tested at VDD = 0 80 100 120 Ω
Vrx-diff-dc Differential RX peak-to-peak voltage Tested at pins 0.6 1.2 V
Vrx-signal-det-diff-pp Signal detect assert level for active data signal SD_TH = F (float),
0101 pattern at 8 Gbps		 180 mVp-p
Vrx-idle-det-diff-pp Signal detect deassert level for electrical idle SD_TH = F (float),
0101 pattern at 8 Gbps		 110 mVp-p
HIGH SPEED OUTPUTS
Vtx-diff-pp Output voltage differential swing Differential measurement with Out_n+ and OUT_n-, terminated by 50Ω to GND, AC-Coupled,
VID = 1 Vp-p,
DEM0 = 1, DEM1 = 0		 0.8 1 1.2 Vp-p
Vtx-de-ratio_3.5 TXde-emphasis ratio VOD = 1 Vp-p,
DEM0 = 0,
DEM1 = R		 −3.5 dB
Vtx-de-ratio_6 TX de-emphasis ratio VOD = 1 Vp-p,
DEM0 = R, DEM1= R		 –6 dB
tTX-DJ Deterministic jitter VID = 800 mV, PRBS15 pattern, 8.0 0.05 Gbps, VOD = 1 V, UIpp EQ = 0x00, DE = 0 dB (no input or output trace loss) 0.05 UIpp
tTX-RJ Random jitter VID = 800 mV, 0101 pattern, 8.0 Gbps, 0.3 VOD = 1 V, ps RMS EQ = 0x00, DE = 0 dB, (no input or output trace loss) 0.3 ps RMS
TTX-RISE-FALL Transmitter rise/fall time 20% to 80% of differential output voltage 35 45 ps
TRF-MISMATCH Transmitter rise/fall mismatch 20% to 80% of differential output voltage 0.01 0.1 UI
RLTX-DIFF Differential return loss 0.05 GHz - 7.5 GHz –15 dB
7.5 GHz - 15 GHz –5 dB
RLTX-CM Common-mode return loss 0.05 GHz - 5 GHz –10 dB
ZTX-DIFF-DC DC differential TX impedance 100 Ω
VTX-CM-AC-PP TX AC common-mode voltage VOD = 1 Vp-p,
DEM0 = 1, DEM1 = 0		 100 mVpp
ITX-SHORT Transmitter short circuit current-limit Total current the transmitter can supply when shorted to VDD or GND 20 mA
TPDEQ Differential propagation delay EQ = 00, (4) 200 ps
TLSK Lane-to-lane skew T = 25°C, VDD = 2.5 V 25 ps
TPPSK Part-to-part propagation delay skew T = 25°C, VDD = 2.5 V 40 ps
EQUALIZATION
DJE1 Residual deterministic jitter at 10.3 Gbps 35-in 4 mil FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 1F'h,
DEM = 0 dB		 0.3 UI
DJE2 Residual deterministic jitter at 10.3 Gbps 10 meters 30 awg cable,
VID = 0.8 Vp-p,
PRBS15, EQ = 2F'h,
DEM = 0 dB		 0.3 UI
DE-EMPHASIS
DJD1 Residual deterministic jitter at 10.3 Gbps 20-in 4 mil FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 00,
VOD = 1 Vp-p,
DEM = −9 dB		 0.1 UI
(1) Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization and are not ensured.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(3) Ensured by device characterization.
(4) Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation delays.

6.6 Electrical Characteristics – Serial Management Bus Interface

Over recommended operating supply and temperature ranges unless other specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL Data, clock input low voltage 0.8 V
VIH Data, clock input high voltage 2.1 3.6 V
IPULLUP Current through pullup resistor or current source High power specification 4 mA
VDD Nominal bus voltage 2.375 3.6 V
ILEAK-Bus Input leakage per bus segment See  (1) –200 200 µA
ILEAK-Pin Input leakage per device pin –15 µA
CI Capacitance for SDA and SCL See (1) (2) 10 pF
RTERM External termination resistance pull to VDD = 2.5 V ± 5% OR 3.3 V ± 10% Pullup VDD = 3.3 V,
See (1) (2) (3)		 2000 Ω
Pullup VDD = 2.5 V,
See (1) (2) (3)		 1000 Ω
(1) Recommended value.
(2) Recommended maximum capacitance load per bus segment is 400pF.
(3) Maximum termination voltage should be identical to the device supply voltage.

6.7 Timing Requirements – Serial Bus Interface Timing Specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FSMB Bus operating frequency ENSMB = VDD (slave mode) 400 kHz
ENSMB = FLOAT (master mode) 280 400 520 kHz
TBUF Bus free time between stop and start condition 1.3 µs
THD:STA Hold time after (repeated) start condition. After this period, the first clock is generated. At IPULLUP, maximum 0.6 µs
TSU:STA Repeated start condition set-up time 0.6 µs
TSU:STO Stop condition set-up time 0.6 µs
THD:DAT Data hold time 0 ns
TSU:DAT Data set-up time 100 ns
TLOW Clock low period 1.3 µs
THIGH Clock high period See (1) 0.6 50 µs
tF Clock/Data fall time See (1) 300 ns
tR Clock/Data rise time See (1) 300 ns
tPOR Time in which a device must be operational after power-on reset See (1) (2) 500 ms
(1) Compatible with SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details.
(2) Ensured by Design. Parameter not tested in production.
DS100KR800 30148002.gif Figure 1. CML Output and Rise and Fall Transition Time
DS100KR800 30148003.gif Figure 2. Propagation Delay Timing Diagram
DS100KR800 30148005.gif Figure 3. SMBus Timing Parameters

6.8 Typical Characteristics

6.8.1 Electrical Performance

DS100KR800 30148027.gif
Figure 4. Power Dissipation (PD) vs Output Differential Voltage (VOD)
DS100KR800 30148029.gif
Figure 6. Output Differential Voltage (VOD = 1 Vp-p) vs Temperature
DS100KR800 30148028.gif
Figure 5. Output Differential Voltage (VOD = 1 Vp-p) vs Supply Voltage (VDD)