SNLS472A January   2014  – June 2017 DS110DF1610

PRODUCTION DATA.  

  1. 1Features
  2. 2Description
  3. 3Revision History
  4. 4Pin Configuration and Functions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings (DS110DF1610)
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Characteristics
    4. 5.4 Electrical Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Device Data Path Operation
        1. 6.3.1.1 AC-Coupled Receiver With Signal Detect
        2. 6.3.1.2 CTLE
        3. 6.3.1.3 Cross Point Switch
        4. 6.3.1.4 DFE With VGA
        5. 6.3.1.5 Clock and Data Recovery
        6. 6.3.1.6 Reference Clock
        7. 6.3.1.7 Differential Driver With FIR Filter
          1. 6.3.1.7.1 Setting the Output VOD
          2. 6.3.1.7.2 Output Driver Polarity Inversion
          3. 6.3.1.7.3 Driver Output Rise/Fall Time
      2. 6.3.2 Debug Features
        1. 6.3.2.1 Pattern Generator
        2. 6.3.2.2 Pattern Checker
        3. 6.3.2.3 Eye Opening Monitor
        4. 6.3.2.4 Interrupt Signals
      3. 6.3.3 Other Features
        1. 6.3.3.1 Lock Sequencer
    4. 6.4 Device Functional Modes
      1. 6.4.1 SMBus Slave Mode
        1. 6.4.1.1 SDA and SDC
        2. 6.4.1.2 Address Line
        3. 6.4.1.3 Device Configuration in SMBus Slave Mode
    5. 6.5 Programming
      1. 6.5.1 Bit Fields in the Register Set
      2. 6.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 6.6 Register Maps
      1. 6.6.1 Shared and Channel Registers
  7. 7Application and Implementation
    1. 7.1 Typical Applications
    2. 7.2 Initialization Setup
      1. 7.2.1 Data Rate Selection (Rate/Sub-Rate Table)
      2. 7.2.2 Data Rate Selection (Manual Programming)
  8. 8Power Supply Recommendations
    1. 8.1 Power Supply Filtering

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings (DS110DF1610)

Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Supply voltage (VDD) –0.5 2.75 V
LVCMOS input/output voltage –0.5 2.75 V
Open-drain I/O supply voltage –0.5 4 V
CML input voltage –0.5 VDD + 0.5 V
CML input current –30 30 mA
Storage temperature, Tstg –40 150 °C
ESD Ratings Human Body Model (HBM) - JESD22-A114F >4 kV
Charged Device Model (CDM) - JESD22-A114F >1 kV
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications

5.2 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
Supply voltage 2.375 2.5 2.625 V
Ambient temperature –10 25 85 °C
SMBus (SDA, SCL), INTERR_IO 2.5 3.6 V

5.3 Thermal Characteristics

over operating free-air temperature range (unless otherwise noted)(1)
BOARD θ JA (°C / W) Ψ JT (°C / W) Ψ JB (°C / W)
JEDEC 18.2 0.7 5.4
8x6 inches 10 layer 7.2 0.3 3.2
8x6 inches 20 layer 6.4 0.3 3.2
8x6 inches 30 layer 6.3 0.3 3.2
(1) For soldering specifications: See product folder at www.ti.com

5.4 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R_baud Input Data Rate Full Rate 8.5 11.3 Gbps
Half Rate 4.25 5.65
Quarter Rate 2.125 2.825
Eighth Rate 1.0625 1.4125
POWER SUPPLY
W Power Consumption per Active Channel CTLE only, 800mVp-p VOD, per channel,
CDR locked		 210 mW
CDR Locking with CTLE only, 800mVp-p VOD,
per channel		 342.8
CTLE and DFE, 800mVp-p VOD, per channel,
CDR locked		 235
CDR Locking with CTLE and DFE, 800mVp-p VOD 367.8
PRBS Checker 57
PRBS Generator 83
WSTATIC Static Power consumption Power applied,
no signals present		 300 mW
LVCMOS
V IH High level input voltage 1.75 VDD V
VIL Low level input voltage GND 0.7 V
VOH High level output voltage IOH = 4mA 2 V
VOL Low level output voltage IOL = –4mA 0.4 V
IIH Input High Leakage current Vinput = VDD,
Open Drain pins		 +30 mA
Vinput = VDD,
JTAG pins, Ref_CLK pins		 +25
Vinput = VDD,
CLK_MON pin		 +50
Vinput = VDD,
GPIO pins, EN_SMB pin		 +75
IIL Input Low Leakage current Vinput = 0V,
Open Drain pins		 –15 mA
Vinput = 0V,
JTAG pins, Ref_CLK pins		 –45
Vinput = 0V,
CLK_MON pin		 –50
Vinput = 0V,
GPIO pins, EN_SMB pin		 –120
RX INPUTS
RRD DC Input Resistance 80 100 120 Ω
VRX-IN Input Differential Voltage 1600 mVPP
Vcm-RX Input common mode Internal coupling cap VRX-IN / 4 VDD – (VRX-IN/ 4) V
TX OUTPUTS
VOD Output Differential Voltage drv_sel_vod[5:0] = 31, DEM, C0 = default 825 1000 1200 mVPP
drv_sel_vod[5:0] = 15, DEM, C0 = default 400 525 675
ΔVOD Step Size for drv_sel_vod Control Default DEM, and FIR settings 32 mVPP
ΔVODVT Change in Output Differentential Voltage due to Change in Temperature and Voltage <15 mVPP
RRd Output Differential Resistance 100 Ω
RRDZ Output Resistance of Shutdown Termination Resistor Resistor connects output pin to VDD 50 Ω
tr, tf Output Rise/Fall Time 20% - 80% using 8T Pattern, fir_sel_edge = default 35 ps
IOS Output Short Circuit Current Differential Driver Output pin short to GND
drv_sel_vod = >4		 –16 mA
RETIMER JITTER SPECS
JTJ Total Output Jitter PRBS-7 pattern, measured to 1e-12
10.3125 Gbps data rate		 8.6
(89)		 ps
(mUI)
PRBS-7 pattern, measured to 1e-12
8.625 Gbps data rate		 9.35
(80.6)
JRJ Output Random Jitter PRBS-7 pattern, measured to 1e-12
10.3125 Gbps data rate		 400
(4.125)		 fs-rms
(mUI-rms)
PRBS-7 pattern, measured to 1e-12
8.625 Gbps data rate		 439
(3.78)
JDJ Output Deterministic Jitter PRBS-7
10.3125 Gbps data rate		 3.15
(33)		 ps
(mUI)
PRBS-7
8.625 Gbps data rate		 3.35
(28.9)
JTRANS Jitter Transfer –6 dB
JPEAK Jitter Peaking <0.1 dB
BWPLL PLL Bandwidth Data Rate = 8.625 Gbps 6.35 MHz
Data Rate = 11.3 Gbps 8.43
RETIMER TIMING SPECS
tD Propagation Delay from Rx inputs to Tx outputs Data Rate = 10.3125Gbps,
No Cross Point		 480 ps
Data Rate = 10.3125 Gbps,
Cross Point enabled		 505 ps
tSK Channel To Channel Skew <80 ps
RECOMMENDED REFERENCE CLOCK SPECS
REFf Input Reference Clock Frequency 25 MHz
125
312.5
REFPPM Reference Clock PPM Tolerance –100 100 PPM
REFTH Reference Clock Input High Threshold Differential mode 100 mV
REFTL Reference Clock Input Low Threshold Differential mode –100 mV
SMBus ELECTRICAL CHARACTERISTICS
VIH Input High Level Voltage SDA and SCL 1.75 VDDIO V
VIL Input Low Level Voltage SDA and SCL GND 0.7 V
CIN Input Pin Capacitance <5 pF
VOL Low Level Output Voltage SDA and SCL
VDDIO = 2.5V
IOL = 2mA		 0.4 V
RECOMMENDED SMBus SWITCHING CHARACTERISTICS
fSCL SCL Clock Frequency 10 100 400 kHz
tHD:DAT Data Hold Time 15 ns
tSU:DAT Data Setup Time 170 ns
RECOMMENDED JTAG SWITCHING CHARACTERISTICS
tTCK TCK Clock Period 100 ns
tSU TDI, TMI Setup Time to TCK 50 ns
tHD TDI, TMS Hold Time to TCK 50 ns
tDLY TCK Falling Edge to TDO 50 ns