The DS125BR401A is an extremely low-power high-performance repeater/redriver designed to support four lanes carrying high speed interface up to 12 Gbps. The B-Side receiver's continuous time linear equalizers (CTLE) provide high frequency boost of up to +24 dB at 6 GHz (12 Gbps) and are capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as backplane traces or twinaxial copper cables. The programmable equalization allows maximum flexibility in the physical placement within the interconnect channel. The A-Side channel has a 10 dB linear equalizer and linear output driver.
The A-Side channel has a settable 3-10 dB linear equalizer coupled to a linear output driver. When operating in SAS-3 and PCIe Gen-3 applications the DS125BR401A preserves transmit signal characteristics allowing the host controller and the end point to negotiate transmit equalizer coefficients. This transparency to the link training protocol aides system level interoperability and minimum latency.
The programmable settings can be applied easily via Terminals, software (SMBus or I2C), or loaded via an external EEPROM. In EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver.
ORDER NUMBER | PACKAGE | BODY SIZE |
---|---|---|
DS125BR401ANJY | WQFN (48) | 10 mm x 5,5 mm |
TERMINAL NAME | TERMINAL NUMBER | I/O, TYPE | TERMINAL DESCRIPTION |
---|---|---|---|
DIFFERENTIAL HIGH SPEED I/O | |||
INB_0+, INB_0- , INB_1+, INB_1-, INB_2+, INB_2-, INB_3+, INB_3- |
45, 44, 43, 42 40, 39, 38, 37 |
I | Inverting and non-inverting CML differential inputs to the equalizer. On-chip 50Ω termination resistor connects INB_n+ to VDD and INB_n- to VDD when enabled. AC coupling required on high-speed I/O |
OUTB_0+, OUTB_0-, OUTB_1+, OUTB_1-, OUTB_2+, OUTB_2-, OUTB_3+, OUTB_3- |
1, 2, 3, 4 5, 6, 7, 8 |
O | Inverting and non-inverting 50Ω driver outputs with de-emphasis. Compatible with AC coupled CML inputs. AC coupling required on high-speed I/O |
INA_0+, INA_0- , INA_1+, INA_1-, INA_2+, INA_2-, INA_3+, INA_3- |
10, 11, 12, 13 15, 16, 17, 18 |
I | Inverting and non-inverting CML differential inputs to the equalizer. On-chip 50Ω termination resistor connects INA_n+ to VDD and INA_n- to VDD when enabled. AC coupling required on high-speed I/O |
OUTA_0+, OUTA_0-, OUTA_1+, OUTA_1-, OUTA_2+, OUTA_2-, OUTA_3+, OUTA_3- |
35, 34, 33, 32 31, 30, 29, 28 |
O | Inverting and non-inverting 50Ω driver outputs. Compatible with AC coupled CML inputs. AC coupling required on high-speed I/O |
CONTROL TERMINALS — SHARED (LVCMOS) | |||
ENSMB | 48 | I, LVCMOS | System Management Bus (SMBus) enable Terminal Tie 1kΩ to VDD = Register Access SMBus Slave mode FLOAT = Read External EEPROM (Master SMBUS Mode) Tie 1kΩ to GND = Terminal Mode |
ENSMB = 1 (SMBus MODE) | |||
SCL | 50 | I, LVCMOS, O, OPEN Drain |
ENSMB Master or Slave mode SMBus clock input Terminal is enabled (slave mode). Clock output when loading EEPROM configuration (master mode). |
SDA | 49 | I, LVCMOS, O, OPEN Drain |
ENSMB Master or Slave mode The SMBus bidirectional SDA Terminal is enabled. Data input or open drain (pull-down only) output. |
AD0-AD3 | 54, 53, 47, 46 | I, LVCMOS | ENSMB Master or Slave mode SMBus Slave Address Inputs. In SMBus mode, these Terminals are the user set SMBus slave address inputs. |
READ_EN | 26 | I, LVCMOS | When using an External EEPROM, a logic low on this terminal starts the load from the external EEPROM |
ENSMB = 0 (TERMINAL MODE) | |||
EQA0, EQA1 EQB0, EQB1 |
20, 19 46, 47 |
I, 4-LEVEL, LVCMOS |
EQA[1:0] and EQB[1:0] control the level of equalization of the A/B directions. The Terminals are defined as EQx[1:0] only when ENSMB is de-asserted (low). Each of the 4 A/B channels have the same level unless controlled by the SMBus control registers. When ENSMB goes high the SMBus registers provide independent control of each lane. The EQB[1:0] Terminals are converted to SMBus AD2, AD3 inputs. See Table 5. |
DEMB0, DEMB1 | 53, 54 | I, 4-LEVEL, LVCMOS |
DEMB[1:0] controls the level of de-emphasis of CHB outputs. The Terminals are defined as DEMB[1:0] only when ENSMB is de-asserted (low). Each of the 4 B channels have the same level unless controlled by the SMBus control registers. When ENSMB goes high the SMBus registers provide independent control of each lane. The DEMB[1:0] Terminals are converted to AD0, AD1 inputs. See Table 7. |
MODE_B | 21 | I, 4-LEVEL, LVCMOS |
MODE_B control Terminal selects operating modes for the INB-OUTB Channels. Tie 1kΩ to GND = GEN 1,2 and SAS 1,2 Float = Auto Mode Select (for PCIe) Tie 20kΩ to GND = SAS-3 and GEN-3 without De-emphasis Tie 1kΩ to VDD = SAS-3 and GEN-3 with De-emphasis See Table 4. |
DEMA0, DEMA1 | 49, 50 | I, 4-LEVEL, LVCMOS |
DEMA[1:0] controls the CHA output amplitude. The Terminals are defined as DEMA[1:0] only when ENSMB is de-asserted (low). Each of the 4 A channels have the same level unless controlled by the SMBus control registers. When ENSMB goes high the SMBus registers provide independent control of each lane and the DEMA[1:0] Terminals are converted to SCL and SDA. See Table 7. |
SD_TH | 26 | I, 4-LEVEL, LVCMOS |
Controls the internal Signal Detect Threshold on the INB-OUTB Channels. For CHB, the signal detect is used to bring the output into and out of IDLE. This allows the OOB signaling to pass with minimal distortion. See Table 3. |
CONTROL TERMINALS — BOTH TERMINAL AND SMBus MODES (LVCMOS) | |||
RXDET | 22 | I, 4-LEVEL, LVCMOS |
The RXDET Terminal controls the receiver detect function. Depending on the input level, a 50Ω or >50KΩ termination to the power rail is enabled. In SAS/SATA system RXDET should be set to a Logic "1" state to keep the termination always enabled. See Table 2. |
RES | 23 | I, 4-LEVEL, LVCMOS |
Reserved: This input must be left Floating. |
VDD_SEL | 25 | I, FLOAT | Controls the internal regulator Float = 2.5V mode Tie GND = 3.3V mode |
PWDN | 52 | I, LVCMOS | Tie High = Low power - power down Tie GND = Normal Operation See Table 2. |
ALL_DONE | 27 | O, LVCMOS | Valid Register Load Status Output HIGH = External EEPROM load failed or incomplete LOW = External EEPROM load passed |
POWER | |||
VIN | 24 | Power | In 3.3V mode, feed 3.3V to VIN In 2.5V mode, leave floating. |
VDD | 9, 14,36, 41, 51 | Power | Power supply Terminals CML/analog 2.5V mode, connect to 2.5V 3.3V mode, connect 0.1 µF cap to each VDD Terminal and GND |
GND | DAP | Power | Ground pad (DAP - die attach pad). |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply Voltage (VDD - 2.5V) | -0.5 | +2.75 | V | |
Supply Voltage (VIN - 3.3V) | -0.5 | +4.0 | V | |
LVCMOS Input/Output Voltage | -0.5 | +4.0 | V | |
CML Input Voltage | -0.5V to (VDD+0.5) | |||
CML Input Current | -30 | +30 | mA |
MIN | MAX | UNIT | ||
---|---|---|---|---|
ESDHBM | HBM, STD - JESD22-A114F | 4 | kV | |
ESDCDM | CDM, STD - JESD22-C101-D | 1 | kV | |
Tstg | Storage Temperature Range | -40 | 125 | °C |
Tsolder | Lead Temperature Range Soldering (4 sec.) (1) | 260 | °C |
MIN | TYP | MAX | UNIT | |
---|---|---|---|---|
Supply Voltage (2.5V mode) | 2.375 | 2.5 | 2.625 | V |
Supply Voltage (3.3V mode) | 3.0 | 3.3 | 3.6 | V |
Ambient Temperature | -40 | 25 | +85 | °C |
SMBus (SDA, SCL) | 3.6 | V | ||
Supply Noise up to 50 MHz(1) | 100 | mVp-p |
THERMAL METRIC(1) | DS125BR401A | UNIT | |
---|---|---|---|
WQFN | |||
54 TERMINALS | |||
RθJA | Junction-to-ambient thermal resistance | 26.6 | °C/W |
RθJCtop | Junction-to-case (top) thermal resistance | 10.8 | |
RθJB | Junction-to-board thermal resistance | 4.4 | |
ψJT | Junction-to-top characterization parameter | 0.2 | |
ψJB | Junction-to-board characterization parameter | 4.3 | |
RθJCbot | Junction-to-case (bottom) thermal resistance | 1.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER | ||||||
IDD | Current Consumption | DEM0 = Float, ,DEM1 = Float EQ = 0, VOD = 0.8VP-P, RXDET = 1, PWDN = 0 |
200 | 280 | mA | |
Power Down Current Consumption | PWDN = 1 | 14 | 27 | mA | ||
VDD | Integrated LDO Regulator | VIN = 3.0 - 3.6 V | 2.375 | 2.5 | 2.625 | V |
LVCMOS / LVTTL DC SPECIFICATIONS | ||||||
Vih25 | High Level Input Voltage | 2.5 V Supply Mode | 1.7 | VDD | V | |
Vih33 | High Level Input Voltage | 3.3 V Supply Mode | 1.7 | VIN | V | |
Vil | Low Level Input Voltage | 0 | 0.7 | V | ||
Voh | High Level Output Voltage (ALL_DONE Terminal) |
Ioh = −4mA | 2.0 | V | ||
Vol | Low Level Output Voltage (ALL_DONE Terminal) |
Iol = 4mA | 0.4 | V | ||
Iih | Input High Current (PWDN Terminal) | VIN = 3.6 V, LVCMOS = 3.6 V |
-15 | +15 | uA | |
Iil | Input Low Current (PWDN Terminal) | VIN = 3.6 V, LVCMOS = 0 V |
-15 | +15 | uA | |
4-LEVEL INPUT DC SPECIFICATIONS | ||||||
Iih | Input High Current with internal resistors (4–level input Terminal) |
VIN = 3.6 V, LVCMOS = 3.6 V |
+20 | +150 | uA | |
Iil | Input Low Current with internal resistors (4–level input Terminal) |
VIN = 3.6 V, LVCMOS = 0 V |
-160 | -40 | uA | |
Vth | Threshold 0 / R | VDD = 2.5V (2.5V supply mode) Internal LDO Disabled See Table 1 for details |
0.45 | V | ||
Threshold R / Float | 1.2 | |||||
Threshold Float / 1 | 2 | |||||
Threshold 0 / R | VIN = 3.3V (3.3V supply mode) Internal LDO Enabled See Table 1 for details. |
0.6 | V | |||
Threshold R / Float | 1.6 | |||||
Threshold Float / 1 | 2.6 | |||||
CML RECEIVER INPUTS (IN_n+, IN_n-) | ||||||
RLRX-diff | RX Differential return loss | SDD11 10 MHz | -19 | dB | ||
SDD11 2 GHz | -14 | |||||
SDD11 6-11.1 GHz | -8 | |||||
RLRX-cm | RX Common mode return loss | 0.05 - 5 GHz | -10 | dB | ||
ZRX-dc | RX DC common mode impedance | Tested at VDD = 2.5 V | 40 | 50 | 60 | Ω |
ZRX-diff-dc | RX DC differential mode impedance | Tested at VDD = 2.5 V | 80 | 100 | 120 | Ω |
VRX-signal-det-diff-pp | Signal detect assert level for active data signal | SD_TH = F (float), 0101 pattern at 12 Gbps |
50 | mVp-p | ||
VRX-idle-det-diff-pp | Signal detect de-assert level for electrical idle | SD_TH = F (float), 0101 pattern at 12 Gbps |
37 | mVp-p | ||
HIGH SPEED OUTPUTS | ||||||
TTX-RISE-FALL | Transmitter rise/fall time (3) | 20% to 80% of differential output voltage | 40 | ps | ||
TRF-MISMATCH | Transmitter rise/fall mismatch | 20% to 80% of differential output voltage | 0.01 | UI | ||
RLTX-DIFF | TX Differential return loss | SDD22 10 MHz - 2 GHz | -15 | dB | ||
SDD22 5.5 GHz | -12 | |||||
SDD22 11.1 GHz | -10 | dB | ||||
RLTX-CM | TX Common mode return loss | 0.05 - 5 GHz | -10 | dB | ||
ZTX-DIFF-DC | DC differential TX impedance | 100 | Ω | |||
ITX-SHORT | Transmitter short circuit current limit | Total current, output shorted to VDD or GND | 20 | mA | ||
VTX-CM-DC-ACTIVE-IDLE-DELTA | Absolute delta of DC common mode voltage during L0 and electrical idle | 100 | mV | |||
VTX-CM-DC-LINE-DELTA | Absolute delta of DC common mode voltage between TX+ and TX- | 25 | mV | |||
HIGH SPEED OUTPUTS (A-CHANNELS) | ||||||
VTXA-diff1-pp | Output Voltage Differential Swing | Differential measurement with OUTA_n+ and OUTA_n-, AC-Coupled and terminated by 50Ω to GND, Inputs AC-Coupled, VID = 600 mVp-p VOD = 001'b (800mV) |
375 | 465 | 600 | mVp-p |
VTXA-diff2-pp | Output Voltage Differential Swing | Differential measurement with OUTA_n+ and OUTA_n-, AC-Coupled and terminated by 50Ω to GND, Inputs AC-Coupled, VID = 1000 mVp-p VOD = 001'b (800mV) |
550 | 675 | 825 | mVp-p |
VTXA-diff3-pp | Output Voltage Differential Swing | Differential measurement with OUTA_n+ and OUTA_n-, AC-Coupled and terminated by 50Ω to GND, Inputs AC-Coupled, VID = 600 mVp-p DEMA[1:0] = 10, VOD = 1300mV |
475 | 600 | 750 | Vp-p |
VTXA-diff4-pp | Output Voltage Differential Swing | Differential measurement with OUTA_n+ and OUTA_n-, AC-Coupled and terminated by 50Ω to GND, Inputs AC-Coupled, VID = 1000 mVp-p VOD = 110'b (1300mV) |
775 | 915 | 1125 | Vp-p |
TTXA-IDLE-DATA | Time to transition to valid differential signal after idle | VID = 1.0 Vp-p, 3 Gbps | 0.04 | ns | ||
TTXA-DATA-IDLE | Time to transition to idle after differential signal | VID = 1.0 Vp-p, 3 Gbps | 0.70 | ns | ||
TPDEQA | Differential propagation delay - Channel A | EQ = Level 1 to Level 4 | 80 | ps | ||
HIGH SPEED OUTPUTS (B-CHANNELS) | ||||||
VTXB-diff1-pp | Output Voltage Differential Swing | Differential measurement with OUTB_n+ and OUTB_n-, AC-Coupled and terminated by 50Ω to GND, Inputs AC-Coupled, VID = 1.0 Vp-p, MODE_B = 1 DEMB1 = 0, DEMB0 = 1(4) |
0.8 | 1.0 | 1.2 | Vp-p |
VTXB-diff2-pp | Output Voltage Differential Swing | Differential measurement with OUTB_n+ and OUTB_n-, AC-Coupled and terminated by 50Ω to GND, Inputs AC-Coupled, VID = 1.0 Vp-p, MODE_B = 0 DEMB1 = 0, DEMB0 = R |
670 | 820 | 930 | mVp-p |
VTXB-diff3-pp | Output Voltage Differential Swing | Differential measurement with OUTB_n+ and OUTB_n-, AC-Coupled and terminated by 50Ω to GND, Inputs AC-Coupled, VID = 1.0 Vp-p, MODE_B = 0 DEMB1 = R, DEMB0 = FLOAT |
950 | 1140 | 1250 | mVp-p |
VTXB-de-ratio_3.5 | TX de-emphasis ratio | VOD = 1.0 Vp-p, DEM0 = 0, DEM1 = R, MODE_B = 0 OUTB_n only Gen 1 & 2 mode |
−3.5 | dB | ||
VTXB-de-ratio_6 | TX de-emphasis ratio | VOD = 1.0 Vp-p, DEM0 = R, DEM1 = R, MODE_B = 0 OUTB_n only in Gen 1 & 2 mode |
−6 | dB | ||
TTXB-IDLE-DATA | Time to transition to valid differential signal after idle | VID = 1.0 Vp-p, 3 Gbps | 3.5 | ns | ||
TTXB-DATA-IDLE | Time to transition to idle after differential signal | VID = 1.0 Vp-p, 3 Gbps | 5.0 | ns | ||
TPDEQB | Differential propagation delay - Channel B | EQ = 00(2) | 135 | ps | ||
EQUALIZATION (A-CHANNELS) | ||||||
DJE1A | Residual deterministic jitter at 6 Gbps | 5” Differential Stripline, 5mil trace width, FR4, VID = 0.8 Vp-p, PRBS15, EQ = 01'h, VOD = 1.3V, DEM = 0 dB |
0.06 | UI | ||
DJE3A | Residual deterministic jitter at 12 Gbps | 5” Differential Stripline, 5mil trace width, FR4, VID = 0.8 Vp-p, PRBS15, EQ = 01'h, VOD = 1.3V, DEM = 0 dB |
0.12 | UI | ||
EQUALIZATION (B-CHANNELS) | ||||||
DJE1B | Residual deterministic jitter at 12 Gbps | 30” Differential Stripline, 5mil trace width, FR4, VID = 0.6 Vp-p, PRBS15, EQ = 07'h, DEM = 0 dB |
0.18 | UI | ||
DJE2B | Residual deterministic jitter at 12 Gbps | 5 meters 30 awg cable, VID = 0.6 Vp-p, PRBS15, EQ = 07'h, DEM = 0 dB |
0.25 | UI | ||
DE-EMPHASIS (B-CHANNELS, GEN 1&2 MODE ONLY) | ||||||
DJD1 | Residual deterministic jitter at 12 Gbps | Input Channel: 20" Differential Stripline, 5mil trace width, FR4, Output Channel: 10” Differential Stripline, 5mil trace width, FR4, VID = 0.6 Vp-p, PRBS15, EQ = 03'h, VOD = 1.0 Vp-p, DEMB = −3.5 dB |
0.1 | UI |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SERIAL BUS INTERFACE DC SPECIFICATIONS | ||||||
VIL | Data, Clock Input Low Voltage | 0.8 | V | |||
VIH | Data, Clock Input High Voltage | 2.1 | 3.6 | V | ||
VOL | Output Low Voltage | SDA or SCL, IOL = 1.25 mA | 0 | 0.36 | V | |
VDD | Nominal Bus Voltage | 2.375 | 3.6 | V | ||
IIH-Terminal | Input Leakage Per Device Terminal | +20 | +150 | µA | ||
IIL-Terminal | Input Leakage Per Device Terminal | -160 | -40 | µA | ||
CI | Capacitance for SDA and SCL | See(1)(2) | < 5 | pF | ||
RTERM | External Termination Resistance pull to VDD = 2.5V ± 5% OR 3.3V ± 10% | Pullup VDD = 3.3V(1)(2)(3) | 2000 | Ω | ||
Pullup VDD = 2.5V(1)(2)(3) | 1000 | Ω |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SERIAL BUS INTERFACE TIMING SPECIFICATIONS | ||||||
FSMB | Bus Operating Frequency | ENSMB = VDD (Slave Mode) | 400 | kHz | ||
ENSMB = FLOAT (Master Mode) | 280 | 400 | 520 | kHz | ||
tFALL | SDA Fall Time | Read operation RPU = 4.7K, Cb < 50pF |
60 | ns | ||
tRISE | SDA Rise Time | Read operation RPU = 4.7K, Cb < 50pF |
140 | ns | ||
tF | Clock/Data Fall Time | See(1) | 300 | ns | ||
tR | Clock/Data Rise Time | See(1) | 1000 | ns |