SNLS466A September   2013  – March 2014 DS125BR401A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Terminal Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics — Serial Management Bus Interface
    7. 6.7 Timing Requirements Serial Bus Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 Functional Datapath Blocks
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Terminal Control Mode:
      2. 7.4.2 SMBus Mode:
      3. 7.4.3 MODE operation with SMBus Registers
    5. 7.5 Signal Conditioning Settings
    6. 7.6 Programming
    7. 7.7 Register Maps
      1. 7.7.1 Transfer Of Data Via The SMBus
      2. 7.7.2 SMBus Transactions
      3. 7.7.3 Writing a Register
      4. 7.7.4 Reading a Register
  8. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Signal Integrity in SAS-3 Applications
      2. 8.1.2 RX-Detect in SAS/SATA Applications
      3. 8.1.3 Signal Integrity in PCIe Applications
      4. 8.1.4 MODE operation with SMBus Registers
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Power Supply Recommendations

Two approaches are recommended to ensure that the DS125BR401A is provided with an adequate power supply. First, the supply (VDD) and ground (GND) Terminals should be connected to power planes routed on adjacent layers of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.1μF bypass capacitor should be connected to each VDD Terminal such that the capacitor is placed as close as possible to the DS125BR401A. Smaller body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in the range of 1 μF to 10 μF should be incorporated in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic.

The DS125BR401A has an optional internal voltage regulator to provide the 2.5V supply to the device. In 3.3V mode operation, the VIN Terminal = 3.3V is used to supply power to the device. The internal regulator will provide the 2.5V to the VDD Terminals of the device and a 0.1uF cap is needed at each of the 5 VDD Terminals for power supply de-coupling (total capacitance should equal 0.5 uF). The VDD_SEL Terminal must be tied to GND to enable the internal regulator. In 2.5V mode operation, the VIN Terminal should be left open and 2.5V supply must be applied to the 5 VDD Terminals to power the device. The VDD_SEL Terminal must be left open (no connect) to disable the internal regulator.

30198706.gifFigure 21. 3.3V or 2.5V Supply Connection Diagram