SNLS426F August   2012  – November 2018 DS125BR800

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Description (cont.)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics: Serial Management Bus Interface
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
      2. 8.3.2 PCIe Signal Integrity
        1. 8.3.2.1 RX-Detect in SAS/SATA (up to 6 Gbps) Applications
          1. 8.3.2.1.1 Signal Detect Control for Datarates above 8 Gbps
        2. 8.3.2.2 MODE Operation with SMBus Registers
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBus Mode
    5. 8.5 Programming
      1. 8.5.1 SMBus Master Mode
      2. 8.5.2 Transfer of Data Via the SMBus
      3. 8.5.3 System Management Bus (SMBus) and Configuration Registers
      4. 8.5.4 SMBus Transactions
      5. 8.5.5 Writing a Register
      6. 8.5.6 Reading a Register
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1 Layout Guidelines

The CML inputs and LPDS outputs have been optimized to work with interconnects using a controlled differential impedance of 85 - 100 Ω. It is preferable to route differential lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias are used the layout must also provide for a low inductance path for the return currents as well. Route the differential signals away from other signals and noise sources on the printed circuit board. See AN-1187 for additional information on LLP packages.

Figure 27 depicts different transmission line topologies which can be used in various combinations to achieve the optimal system performance. Impedance discontinuities at the differential via can be minimized or eliminated by increasing the swell around each hole and providing for a low inductance return current path. When the via structure is associated with thick backplane PCB, further optimization such as back drilling is often used to reduce the deterimential high frequency effects of stubs on the signal path.