SNLS398H January   2012  – February 2018 DS125DF410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Typical Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 Signal Detect
      3. 7.3.3 CTLE
      4. 7.3.4 DFE
      5. 7.3.5 Clock and Data Recovery
      6. 7.3.6 Output Driver
      7. 7.3.7 Device Configuration
        1. 7.3.7.1 Rate and Subrate Setting
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Master Mode and SMBus Slave Mode
      2. 7.4.2 Address Lines <ADDR_[3:0]>
      3. 7.4.3 SDA and SDC
      4. 7.4.4 Standards-Based Modes
        1. 7.4.4.1 Ref_mode 3 Mode (Reference Clock Required)
        2. 7.4.4.2 False Lock Detector Setting
        3. 7.4.4.3 Reference Clock In
        4. 7.4.4.4 Reference Clock Out
        5. 7.4.4.5 Driver Output Voltage
        6. 7.4.4.6 Driver Output De-Emphasis
        7. 7.4.4.7 Driver Output Rise/Fall Time
        8. 7.4.4.8 INT
        9. 7.4.4.9 LOCK_3, LOCK_2, LOCK_1, and LOCK_0
    5. 7.5 Programming
      1. 7.5.1  SMBus Strap Observation
      2. 7.5.2  Device Revision and Device ID
      3. 7.5.3  Control/Shared Register Reset
      4. 7.5.4  Interrupt Channel Flag Bits
      5. 7.5.5  SMBus Master Mode Control Bits
      6. 7.5.6  Resetting Individual Channels of the Retimer
      7. 7.5.7  Interrupt Status
      8. 7.5.8  Overriding the CTLE Boost Setting
      9. 7.5.9  Overriding the VCO Search Values
      10. 7.5.10 Overriding the Output Multiplexer
      11. 7.5.11 Overriding the VCO Divider Selection
      12. 7.5.12 Using the PRBS Generator
      13. 7.5.13 Using the Internal Eye Opening Monitor
      14. 7.5.14 Overriding the DFE Tap Weights and Polarities
      15. 7.5.15 Enabling Slow Rise/Fall Time on the Output Driver
      16. 7.5.16 Inverting the Output Polarity
      17. 7.5.17 Overriding the Figure of Merit for Adaptation
      18. 7.5.18 Setting the Rate and Subrate for Lock Acquisition
      19. 7.5.19 Setting the Adaptation/Lock Mode
      20. 7.5.20 Initiating Adaptation
      21. 7.5.21 Setting the Reference Enable Mode
      22. 7.5.22 Overriding the CTLE Settings Used for CTLE Adaptation
      23. 7.5.23 Setting the Output Differential Voltage
      24. 7.5.24 Setting the Output De-Emphasis Setting
    6. 7.6 Register Maps
      1. 7.6.1 Register Information
      2. 7.6.2 Bit Fields in the Register Set
      3. 7.6.3 Writing to and Reading from the Control/Shared Registers
      4. 7.6.4 Channel Select Register
      5. 7.6.5 Reading to and Writing from the Channel Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.5 Reading to and Writing from the Channel Registers

Each of the four channels has a complete set of channel registers associated with it. The channel registers or the control/shared registers are selected by channel select register 0xff. The settings in this register control the target for subsequent register reads and writes until the contents of register 0xff are explicitly changed by a register write to register 0xff. As noted, there is only one register with an address of 0xff, the channel select register.

Table 16. Channel Registers

Address (Hex)BITSDEFAULT VALUE (Hex)MODEEEPROMFIELD NAMEDESCRIPTION
0 7:4 0 RW N RESERVED
3 0 RW N RST_CORE 1: Reset core state machine
0: Normal Operation
2 0 RW N RST_REGS 1: Resets channel registers, restores default values
0: Normal Operation
1 0 RW N RST_REFCLK 1: Reset reference clock domain
0: Normal Operation
0 0 RW N RST_VCO 1: Reset VCO DIV clock domain
0: Normal Operation
1 7:5 0 RW N RESERVED
4 0 R N CDR_LOCK_LOSS_INT 1: indicates loss of CDR lock after having acquired it.
Bit clears on read.
3:1 0 R N RESERVED
0 0 R N SIG_DET_LOSS_INT Loss of signal indicator.
Bit is set once signal is acquired and then lost.
2 7:0 0x0 R N cdr_status CDR Status [7:0]
Bit[7] = PPM Count met
  • 1: The data rate is within the specified PPM tolerance (typically around ±1000 ppm unless specified otherwise in Reg 0x64).
  • 0: Error: PPM tolerance exceeded.

Bit[6] = Auto Adapt Complete
  • 1: CTLE auto-adaption is complete.
  • 0: CTLE auto-adaption in progress.

Bit[5] = Fail Lock Check
  • 1: Signal quality and amplitude level is not sufficient for lock.
  • 0: Signal quality and amplitude level is sufficient for CDR lock.

Bit[4] = Lock
  • When asserted, indicates CDR is locked to the incoming signal.

Bit[3] = CDR Lock
  • When asserted, indicates CDR is locked to the incoming signal (same status as bit 4).

Bit[2] = Single Bit Limit Reached
  • 1: Number of bit transitions to acquire CDR lock has been met.
  • 0: Not enough bit transitions within the CDR lock time window to declare lock.

Bit[1] = Comp LPF High
  • 1: Data rate exceeds the VCO upper limit, based on loop filter comparator voltage.
  • 0 = Data rate is within VCO upper limit.

Bit[0] = Comp LPF Low
  • 1: Data rate is below the VCO lower limit, based on loop filter comparator voltage.
  • 0 = Data rate is within VCO lower limit.
3 7 0 RW Y EQ_BST0[1] This register can be used to force an EQ boost setting if used in conjunction with channel register 0x2D[3].
6 0 RW Y EQ_BST0[0]
5 0 RW Y EQ_BST1[1]
4 0 RW Y EQ_BST1[0]
3 0 RW Y EQ_BST2[1]
2 0 RW Y EQ_BST2[0]
1 0 RW Y EQ_BST3[1]
0 0 RW Y EQ_BST3[0]
4 7:0 0 RW N RESERVED
5 7:0 0 RW N RESERVED
6 7:0 0 RW N RESERVED
7 7:0 0 RW N RESERVED
8 7:5 0 RW Y RESERVED
4 0 RW Y CDR_CAP_DAC_START4 Starting VCO Cap Dac Setting 0
3 0 RW Y CDR_CAP_DAC_START3 Starting VCO Cap Dac Setting 0
2 0 RW Y CDR_CAP_DAC_START2 Starting VCO Cap Dac Setting 0
1 0 RW Y CDR_CAP_DAC_START1 Starting VCO Cap Dac Setting 0
0 0 RW Y CDR_CAP_DAC_START0 Starting VCO Cap Dac Setting 0
9 7 0 RW Y DIVSEL_VCO_CAP_OV Enable bit to override cap_cnt with value in register 0x0B[4:0]
6 0 RW Y SET_CP_LVL_LPF_OV Enable bit to override lpf_dac_val with value in register 0x1F[4:0]
5 0 RW Y BYPASS_PFD_OV Enable bit to override sel_retimed_loopthru and sel_raw_loopthru with values in reg 0x1E[7:5]
4 0 RW Y EN_FD_PD_VCO_PDIQ_OV Enable bit to override en_fd, pd_pd, pd_vco, pd_pdiq with reg 0x1E[0], reg 0x1E[2], reg 0x1C[0], reg 0x1C[1]
3 0 RW Y EN_PD_CP_OV Enable bit to override pd_fd_cp and pd_pd_cp with value in reg 0x1B[1:0]
2 0 RW Y DIVSEL_OV Enable bit to override divsel with value in reg 0x18[6:4]
1: Override enable
0: Normal operation
1 0 RW Y EN_FLD_OV Enable to override pd_fld with value in reg 0x1E[1]
0 0 RW Y PFD_LOCK_MODE_SM Enable FD in lock state
A 7 0 RW Y SBT_EN Enable bit to override sbt_en with value in reg 0x1D[7]
6 0 RW Y EN_IDAC_PD_CP_OV Enable bit to overridephase detector charge pump settings with reg 0x1C[7:5]
EN_IDAC_FD_CP_OV Enable bit to override frequency detector charge pump settings with reg 0x1C[4:2]
5 0 RW Y DAC_LPF_HIGH_PHASE_OV
DAC_LPF_LOW_PHASE_OV		 Enable bit to override loop filter comparator trip voltage with reg 0x16[7:0]
4 1 RW Y EN150_LPF_OV Enable bit to override en150_lpf with value in reg 0x1F[6]
3 0 RW N CDR_RESET_OV Enable bit to override CDR reset with reg 0x0A[2]
2 0 RW N CDR_RESET_SM 1: CDR is put into reset
0: normal CDR operation
1 0 RW N CDR_LOCK_OV Enable CDR lock signal override with reg 0x0A[0]
0 0 RW N CDR_LOCK CDR lock signal override bit
B 7 0 RW Y RESERVED
6 0 RW Y RESERVED
5 0 RW Y RESERVED
4 0 RW Y CAP_DAC_START1[4] Starting VCO cap dac setting 1
3 1 RW Y CAP_DAC_START1[3] Starting VCO cap dac setting 1
2 1 RW Y CAP_DAC_START1[2] Starting VCO cap dac setting 1
1 1 RW Y CAP_DAC_START1[1] Starting VCO cap dac setting 1
0 1 RW Y CAP_DAC_START1[0] Starting VCO cap dac setting 1
C 7:4 0 RW N RESERVED
3 1 RW Y SINGLE_BIT_LIMIT_CHECK_ON 1: Normal operation, device checks for single bit transitions as a gate to achieving CDR lock
2 0 RW Y RESERVED
1 0 RW Y RESERVED
0 0 RW Y RESERVED
D 7:6 0 RW Y RESERVED
5 0 RW Y PRBS_PATT_SHIFT_EN PRBS Generator Clock Enable
  • 1: Enabled
  • 0: Disabled
4:0 0 RW Y RESERVED
E 7:0 0x93 RW N RESERVED
F 7:0 0x69 RW N RESERVED
10 7:0 0x3A RW Y RESERVED
11 7 0 RW Y EOM_SEL_VRANGE[1] Manually set the EOM vertical range, used with channel register 0x2C[6]:
00: ±100 mV
01: ±200 mV
10: ±300 mV
11: ±400 mV
6 0 RW Y EOM_SEL_VRANGE[0]
5 1 RW Y EOM_PD 1: Normal operation
4 0 RW N RESERVED
3 0 RW Y DFE_TAP2_POL Bit forces DFE tap 2 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
2 0 RW Y DFE_TAP3_POL Bit forces DFE tap 3 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
1 0 RW Y DFE_TAP4_POL Bit forces DFE tap 4 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
0 0 RW Y DFE_TAP5_POL Bit forces DFE tap 5 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
12 7 1 RW Y DFE_TAP1_POL Bit forces DFE tap 1 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
6 1 RW N RESERVED
5 1 RW Y DFE_SEL_NEG_GM
4 0 RW Y DFE_WT1[4] Bits force DFE tap 1 weight, manual DFE operation required to take effect
3 0 RW Y DFE_WT1[3]
2 0 RW Y DFE_WT1[2]
1 0 RW Y DFE_WT1[1]
0 0 RW Y DFE_WT1[0]
13 7 0 RW N RESERVED
6 0 RW Y RESERVED
5 1 RW Y RESERVED
4 1 RW Y EQ_EN_DC_OFF 1: Normal operation
3 0 RW Y RESERVED
2 0 RW Y EQ_LIMIT_EN 1: Configures the final stage of the equalizer to be a limiting stage.
0: Normal operation, final stage of the equalizer is configured to be a linear stage.
1 0 RW Y RESERVED
0 0 RW Y RESERVED
14 7 0 RW Y EQ_SD_PRESET 1: Forces signal detect HIGH, and force enables the channel. Should not be set if bit 6 is set.
0: Normal Operation.
6 0 RW Y EQ_SD_RESET 1: Forces signal detect LOW and force disables the channel. Should not be set if bit 7 is set.
0: Normal Operation.
5 0 RW Y EQ_REFA_SEL1 Controls the signal detect assert levels.
4 0 RW Y EQ_REFA_SEL0
3 0 RW Y EQ_REFD_SEL1 Controls the signal detect de-assert levels.
2 0 RW Y EQ_REFD_SEL0
1:0 0 RW N RESERVED
15 7 0 RW Y DFE_FORCE_EN Enables manual DFE tap settings
6 0 RW Y drv_dem_range Driver De-emphasis Range
5 0 RW Y RESERVED
4 1 RW Y RESERVED
3 0 RW N DRV_PD 1: Powers down the high speed driver
0: Normal operation
2 0 RW Y DRV_DEM2 Driver De-emphasis Setting[2:0]
1 0 RW Y DRV_DEM1
0 0 RW Y DRV_DEM0
16 7:0 0x7A RW Y RESERVED
17 7:0 0x36 RW Y RESERVED
18 7 0 RW N RESERVED
6 1 RW Y PDIQ_SEL_DIV2 These bits will force the divider setting if 0x09[2] is set.
000: Divide by 1
001: Divide by 2
010: Divide by 4
011: Divide by 8
100: Divide by 16
All other values are reserved.
5 0 RW Y PDIQ_SEL_DIV1
4 0 RW Y PDIQ_SEL_DIV0
3 0 RW N RESERVED
2 0 RW N DRV_SEL_SLOW
1:0 0 RW N RESERVED
19 7:6 0x23 RW N RESERVED
5:0 RW Y RESERVED
1A 7:4 0x0 RW Y RESERVED
3:0 0x0 RW N RESERVED
1B 7:2 0 RW N RESERVED
1 1 RW Y CP_EN_CP_PD 1: Normal operation (phase detector charge pump enabled)
0 1 RW Y CP_EN_CP_FD 1: Normal operation (frequency detector charge pump enabled)
1C 7 0 RW Y EN_IDAC_PD_CP2 Phase detector charge pump setting. MSB located in channel register 0x0C[0]. Override bit required for these bits to take effect
6 0 RW Y EN_IDAC_PD_CP1
5 1 RW Y EN_IDAC_PD_CP0
4 0 RW Y EN_IDAC_FD_CP2 Frequency detector charge pump setting. MSB located in channel register 0x0C[1]. Override bit required for these bits to take effect
3 0 RW Y EN_IDAC_FD_CP1
2 1 RW Y EN_IDAC_FD_CP0
1:0 0 RW Y RESERVED
1D 7 0 RW Y SBT_EN SBT enable override
0: Normal operation
6:0 0 RW N RESERVED
1E 7 1 RW Y PFD_SEL_DATA_MUX2 For these values to take effect, register 0x09[5] must be set to 1.
000: Raw Data*
001: Retimed Data
100: Pattern Generator
111: Mute
All other values are reserved.
6 1 RW Y PFD_SEL_DATA_MUX1
5 1 RW Y PFD_SEL_DATA_MUX0
4 0 RW N PRBS_EN 1: Enable PRBS Generator
3 1 RW Y DFE_PD This bit must be cleared for the DFE to be functional in any adapt mode.
0: DFE enabled
1: DFE disabled
2 0 RW Y PFD_PD_PD PFD phase detector power down override
1 0 RW Y PFD_EN_FLD PFD enable FLD override
0 1 RW Y PFD_EN_FD PFD enable frequency detector override
1F 7 0 RW Y RESERVED
6 1 RW Y LPF_EN_150 When reg_0A[4]=1, this bit will change the loop filter resistance.
1 - 1500 Ω
0 - 750 Ω
5 0 RW N RESERVED
4 1 RW N lpf_dac_val[4] lpf_dac_val over-ride
3 0 RW N lpf_dac_val[3] lpf_dac_val over-ride
2 1 RW N lpf_dac_val[2] lpf_dac_val over-ride
1 0 RW N lpf_dac_val[1] lpf_dac_val over-ride
0 1 RW N lpf_dac_val[0] lpf_dac_val over-ride
20 7 0 RW Y DFE_WT5[3] Bits force DFE tap 5 weight, manual DFE operation required to take effect
6 0 RW Y DFE_WT5[2]
5 0 RW Y DFE_WT5[1]
4 0 RW Y DFE_WT5[0]
3 0 RW Y DFE_WT4[3] Bits force DFE tap 4 weight, manual DFE operation required to take effect
2 0 RW Y DFE_WT4[2]
1 0 RW Y DFE_WT4[1]
0 0 RW Y DFE_WT4[0]
21 7 0 RW Y DFE_WT3[3] Bits force DFE tap 3 weight, manual DFE operation required to take effect
6 0 RW Y DFE_WT3[2]
5 0 RW Y DFE_WT3[1]
4 0 RW Y DFE_WT3[0]
3 0 RW Y DFE_WT2[3] Bits force DFE tap 2 weight, manual DFE operation required to take effect
2 0 RW Y DFE_WT2[2]
1 0 RW Y DFE_WT2[1]
0 0 RW Y DFE_WT2[0]
22 7:0 0 RW N RESERVED
23 7 0 RW N EOM_GET_HEO_VEO_OV 1: Override enable for manual control of the HEO/VEO trigger
0: Normal operation
6 1 RW Y DFE_OV 1: Normal operation, DFE must be enabled in channel register 0x1E[3]
5:0 0 RW N RESERVED
24 7 0 RW N FAST_EOM 1: Enables fast EOM mode for fully eye capture. In this mode the phase DAC and voltage DAC of the EOM are automatically incremented through a 64 x 64 matrix. Values for each point are stored in channel registers 25 and 26.
6 0 RW N DFE_EQ_ERROR_NO_LOCK DFE/CTLE SM quit due to loss of lock
5 0 RW N GET_HEO_VEO_ERROR_
NO_HITS		 GET_HEO_VEO sees no hits at zero crossing
4 0 RW N GET_HEO_VEO_ERROR_
NO_OPENING		 GET_HEO_VEO cannot see a vertical eye opening
3 0 RW N RESERVED
2 0 RW N DFE_ADAPT 1: Manually start DFE adaption, self-clearing.
0: Normal operation
1 0 RW N EOM_GET_HEO_VEO 1: Manually triggers a HEO/VEO measurement. Must be enabled with channel register 0x23[7].
0 0 RW N EOM_START 1: Starts EOM counter, self clearing
25 7 0 R N EOM_COUNT15 MSBs of EOM counter
6 0 R N EOM_COUNT14
5 0 R N EOM_COUNT13
4 0 R N EOM_COUNT12
3 0 R N EOM_COUNT11
2 0 R N EOM_COUNT10
1 0 R N EOM_COUNT9
0 0 R N EOM_COUNT8
26 7 0 R N EOM_COUNT7 LSBs of EOM counter
6 0 R N EOM_COUNT6
5 0 R N EOM_COUNT5
4 0 R N EOM_COUNT4
3 0 R N EOM_COUNT3
2 0 R N EOM_COUNT2
1 0 R N EOM_COUNT1
0 0 R N EOM_COUNT0
27 7 0 R N HEO7 HEO value, requires CDR to be locked for valid measurement
6 0 R N HEO6
5 0 R N HEO5
4 0 R N N HEO4
3 0 R HEO3
2 0 R N HEO2
1 0 R N HEO1
0 0 R N HEO0
28 7 0 R N VEO7 VEO value, requires CDR to be locked for valid measurement
6 0 R N VEO6
5 0 R N VEO5
4 0 R N VEO4
3 0 R N VEO3
2 0 R N VEO2
1 0 R N VEO1
0 0 R N VEO0
29 7 0 RW N RESERVED
6 0 R N EOM_VRANGE_SETTING1 Use these bits to read back the EOM voltage range setting:
00: ±100 mV
01: ±200 mV
10: ±300 mV
11: ±400 mV
5 0 R N EOM_VRANGE_SETTING0
4:0 0 RW N RESERVED
2A 7 0 RW Y EOM_TIMER_THR7 Controls the amount of time the EOM samples each point in the eye for. The total counter bit width is 16-bits. This register is the upper 8-bits. The counter counts in 32-bit words. Therefore, the total number of bits is 32 times this value
6 0 RW Y EOM_TIMER_THR6
5 1 RW Y EOM_TIMER_THR5
4 1 RW Y EOM_TIMER_THR4
3 0 RW Y EOM_TIMER_THR3
2 0 RW Y EOM_TIMER_THR2
1 0 RW Y EOM_TIMER_THR1
0 0 RW Y EOM_TIMER_THR0
2B 7:6 0 RW N RESERVED
5:4 0 RW Y RESERVED
3 0 RW Y EOM_MIN_REQ_HITS3 These bits set the number of hits for a particular phase and voltage location in the EOM before the EOM will indicate a hit has occurred. This filtering only affects the HEO measurement. Filter threshold ranges from 0 to 15 hits.
2 0 RW Y EOM_MIN_REQ_HITS2
1 0 RW Y EOM_MIN_REQ_HITS1
0 0 RW Y EOM_MIN_REQ_HITS0
2C 7 0 RW N RESERVED
6 1 RW Y VEO_SCALE Scale VEO based on EOM vrange
5 1 RW Y DFE_SM_FOM1 00: not valid
01: SM uses only HEO
10: SM uses only VEO
11: SM uses both HEO and VEO
4 1 RW Y DFE_SM_FOM0
3 0 RW Y DFE_ADAPT_COUNTER3 DFE look-beyond count.
2 0 RW Y DFE_ADAPT_COUNTER2
1 1 RW Y DFE_ADAPT_COUNTER1
0 0 RW Y DFE_ADAPT_COUNTER0
2D 7 1 RW Y RESERVED
6 0 RW Y RESERVED
5 0 RW Y RESERVED
4 0 RW Y RESERVED
3 0 RW Y EQ_BST_OV Allow override control of the EQ setting by writing to channel register 0x03. Not recommended for normal operation.
2 0 RW Y DRV_SEL_VOD2 Controls the VOD levels of the high speed drivers
1 0 RW Y DRV_SEL_VOD1
0 0 RW Y DRV_SEL_VOD0
2E 7:00 0 RW N RESERVED
2F 7 0 RW Y RATE1 4 bits determine standard. Refer to Table 2.
6 0 RW Y RATE0
5 0 RW Y SUBRATE1
4 0 RW Y SUBRATE0
3 0 RW Y INDEX_OV If this bit is set to 1, reg 0x13 is to be used as a 5 bit index to the [31:0] array of EQ settings.
2 1 RW Y EN_PPM_CHECK 1: PPM check to be used as a qualifier when performing lock detect
1 1 RW Y EN_FLD_CHECK For default ref_mode 3:
0: FLD is enabled
1: FLD is disabled
0 0 RWSC N CTLE_ADAPT Starts CTLE adaption, self-clearing
30 7 0 RW N RESERVED
6 0 RW N RESERVED
5 0 R N EOM_VRANGE_LIMIT_ERROR
4 0 R N HEO_VEO_INTERRUPT Requires that channel register 0x36[6] be set.
1: Indicates that HEO/VEO dropped below the limits set in channel register 0x76 This bit is cleared after reading. This bit will stay set until it has been cleared by reading.
3 0 RW Y PRBS_EN_DIG_CLK This bit enables the clock to operate the PRBS generator and/or the PRBS checker. Toggling this bit is the primary method to reset the PRBS pattern generator and PRBS checker.
2 0 RW N RESERVED
1 0 RW Y PRBS_PATTERN_SEL1 Selects the PRBS generator pattern to output. Requires that the pattern generator be configured properly.
00: PRBS-7
01: PRBS-9
10: PRBS-15
11: PRBS-31
0 0 RW Y PRBS_PATTERN_SEL0
31 7 0 RW Y RESERVED
6 0 RW Y ADAPT_MODE1 00: no adaption
01: adapt CTLE only
10: adapt CTLE until optimal, then DFE, then CTLE again
11: adapt CTLE until lock, then DFE, then EQ until optimal
5 1 RW Y ADAPT_MODE0
4 0 RW Y EQ_SM_FOM1 00: not valid
01: SM uses HEO only
10: SM uses VEO only
11: SM uses both HEO and VEO
3 0 RW Y EQ_SM_FOM0
2 0 RW N RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
32 7 0 RW Y HEO_INT_THRESH3 These bits set the threshold for the HEO and VEo interrupt. Each threshold bit represents 8 counts of HEO or VEO.
6 0 RW Y HEO_INT_THRESH2
5 0 RW Y HEO_INT_THRESH1
4 1 RW Y HEO_INT_THRESH0
3 0 RW Y VEO_INT_THRESH3
2 0 RW Y VEO_INT_THRESH2
1 0 RW Y VEO_INT_THRESH1
0 1 RW Y VEO_INT_THRESH0
33 7 1 RW Y HEO_THRESH3 In adapt mode 3, the register sets the minimum HEO and VEO required for CTLE adaption, before starting DFE adaption. This can be a max of 15.
6 0 RW Y HEO_THRESH2
5 0 RW Y HEO_THRESH1
4 0 RW Y HEO_THRESH0
3 1 RW Y VEO_THRESH3
2 0 RW Y VEO_THRESH2
1 0 RW Y VEO_THRESH1
0 0 RW Y VEO_THRESH0
34 7 0 RW N PPM_ERR_RDY 1: Indicates that a PPM error count is read to be read from channel register 0x3B and 0x3C
6 0 RW Y LOW_POWER_MODE_DISABLE By default, all blocks (except signal detect) power down after 100ms after signal detect goes low.
5 1 RW Y LOCK_COUNTER1 After achieving lock, the CDR continues to monitor the lock criteria. If the lock criteria fail, the lock is checked for a total of N number of times before declaring an out of lock condition, where N is set by this the value in these registers, with a max value of +3, for a total of 4. If during the N lock checks, lock is regained, then the lock condition is left HI, and the counter is reset back to zero.
4 1 RW Y LOCK_COUNTER0
3 1 RW Y DFE_MAX_TAP2_5[3] These four bits are used to set the maximum value by which DFE taps 2-5 are able to adapt with each subsequent adaptation. Same used for both polarities.
2 1 RW Y DFE_MAX_TAP2_5[2]
1 1 RW Y DFE_MAX_TAP2_5[1]
0 1 RW Y DFE_MAX_TAP2_5[0]
35 7 0 RW Y DATA_LOCK_PPM1 Modifies the value of the ppm delta tolerance from channel register 0x64:
00 - ppm_delta[7:0] =1 x ppm_delta[7:0]
01 - ppm_delta[7:0] =1 x ppm_delta[7:0] + ppm_delta[3:1]
10 - ppm_delta[7:0] =2 x ppm_delta[7:0]
11 - ppm_delta[7:0] =2 x ppm_delta[7:0] + ppm_delta[3:1]
6 0 RW Y DATA_LOCK_PPM0
5 0 RW N GET_PPM_ERROR Get ppm error from ppm_count - clears when done. Normally updates continuously, but can be manually triggered with read value from channel register 0x3B and 0x3C
4 1 RW Y DFE_MAX_TAP1[4] Determines max tap limit for DFE tap 1
3 1 RW Y DFE_MAX_TAP1[3]
2 1 RW Y DFE_MAX_TAP1[2]
1 1 RW Y DFE_MAX_TAP1[1]
0 1 RW Y DFE_MAX_TAP1[0]
36 7 0 RW Y RESERVED
6 0 RW Y HEO_VEO_INT_EN 1: Enable HEO/VEO interrupt capability
5 1 RW Y REF_MODE1 11: Fast_lock all cap dac ref clock enabled (recommended)
10: constrained cap dac, ref clock enabled
01: referenceless constained cap dac
00: referenceless all cap dac
4 1 RW Y REF_MODE0
3 0 RW Y RESERVED
2 0 RW Y CDR_CAP_DAC_RNG_OV Over-ride enable for Cap DAC range
1 0 RW Y cdr_cap_dac_rng[1] Sets the stop value based on start value - (rng+1):
11:stop = start - 4
10: stop = start - 3
01: stop = start - 2
00: stop = start - 1
0 1 RW Y cdr_cap_dac_rng[0]
37 7 0 R N CTLE_STATUS7 Feature is reserved for future use
6 0 R N CTLE_STATUS6
5 0 R N CTLE_STATUS5
4 0 R N CTLE_STATUS4
3 0 R N CTLE_STATUS3
2 0 R N CTLE_STATUS2
1 0 R N CTLE_STATUS1
0 0 R N CTLE_STATUS0
38 7 0 R N DFE_STATUS7 Feature is reserved for future use
6 0 R N DFE_STATUS6
5 0 R N DFE_STATUS5
4 0 R N DFE_STATUS4
3 0 R N DFE_STATUS3
2 0 R N DFE_STATUS2
1 0 R N DFE_STATUS1
0 0 R N DFE_STATUS0
39 7 0 RW N RESERVED
6 0 RW Y EOM_RATE1 With eom_ov=1, these bits control the Eye Monitor Rate:
11: Use for Full Rate, Fastest
10 : Use for 1/2 Rate
01: Use for 1/4 Rate
00: Use for 1/8 Rate, Slowest
5 0 RW Y EOM_RATE0
4 0 RW Y START_INDEX4 Start index for EQ adaptation
3 0 RW Y START_INDEX3
2 0 RW Y START_INDEX2
1 0 RW Y START_INDEX1
0 0 RW Y START_INDEX0
3A 7 1 RW Y FIXED_EQ_BST0[1] During adaptation, if the divider setting is >2, then a fixed EQ setting from this register will be used. However, if channel register 0x6F[7] is enabled, then an EQ adaptation will be performed instead
6 0 RW Y FIXED_EQ_BST0[0]
5 1 RW Y FIXED_EQ_BST1[1]
4 0 RW Y FIXED_EQ_BST1[0]
3 0 RW Y FIXED_EQ_BST2[1]
2 1 RW Y FIXED_EQ_BST2[0]
1 0 RW Y FIXED_EQ_BST3[1]
0 1 RW FIXED_EQ_BST3[0]
3B 7 0 R N RESERVED
6 0 R N RESERVED
5 0 R N RESERVED
4 0 R N RESERVED
3 0 R N RESERVED
2 0 R N RESERVED
1 0 R N RESERVED
0 0 R N RESERVED
3C 7 0 R N RESERVED
6 0 R N RESERVED
5 0 R N RESERVED
4 0 R N RESERVED
3 0 R N RESERVED
2 0 R N RESERVED
1 0 R N RESERVED
0 0 R N RESERVED
3D 7 0 RW Y RESERVED
6 0 RW Y RESERVED
5 0 RW Y RESERVED
4 0 RW Y RESERVED
3 0 RW Y RESERVED
2 0 RW Y RESERVED
1 0 RW Y RESERVED
0 0 RW Y RESERVED
3E 7 1 RW Y HEO_VEO_LOCKMON_EN Enable HEO/VEO lock monitoring.
6 0 RW Y RESERVED
5 0 RW Y RESERVED
4 0 RW Y RESERVED
3 0 RW Y RESERVED
2 0 RW Y RESERVED
1 0 RW Y RESERVED
0 0 RW Y RESERVED
3F 7 0 RW Y RESERVED
6 0 RW Y RESERVED
5 0 RW Y RESERVED
4 0 RW Y RESERVED
3 0 RW Y RESERVED
2 0 RW Y RESERVED
1 0 RW Y RESERVED
0 0 RW Y RESERVED
40-5F CTLE Settings for adaption – see Table 11
60 7 0 RW Y GRP0_OV_CNT7 Group 0 count LSB
6 0 RW Y GRP0_OV_CNT6
5 0 RW Y GRP0_OV_CNT5
4 0 RW Y GRP0_OV_CNT4
3 0 RW Y GRP0_OV_CNT3
2 0 RW Y GRP0_OV_CNT2
1 0 RW Y GRP0_OV_CNT1
0 0 RW Y GRP0_OV_CNT0
61 7 0 RW Y CNT_DLTA_OV_0 Override enable for group 0 manual data rate selection
6 0 RW Y GRP0_OV_CNT14 Group 0 count MSB
5 0 RW Y GRP0_OV_CNT13
4 0 RW Y GRP0_OV_CNT12
3 0 RW Y GRP0_OV_CNT11
2 0 RW Y GRP0_OV_CNT10
1 0 RW Y GRP0_OV_CNT9
0 0 RW Y GRP0_OV_CNT8
62 7 0 RW Y GRP1_OV_CNT7 Group 1 count LSB
6 0 RW Y GRP1_OV_CNT6
5 0 RW Y GRP1_OV_CNT5
4 0 RW Y GRP1_OV_CNT4
3 0 RW Y GRP1_OV_CNT3
2 0 RW Y GRP1_OV_CNT2
1 0 RW Y GRP1_OV_CNT1
0 0 RW Y GRP1_OV_CNT0
63 7 0 RW Y CNT_DLTA_OV_1 Override enable for group 1 manual data rate selection
6 0 RW Y GRP1_OV_CNT14 Group 1 count MSB
5 0 RW Y GRP1_OV_CNT13
4 0 RW Y GRP1_OV_CNT12
3 0 RW Y GRP1_OV_CNT11
2 0 RW Y GRP1_OV_CNT10
1 0 RW Y GRP1_OV_CNT9
0 0 RW Y GRP1_OV_CNT8
64 7 0 RW Y GRP0_OV_DLTA3 Sets the PPM delta tolerance for the PPM counter lock check for group 0. Must also program channel register 0x67[7].
6 0 RW Y GRP0_OV_DLTA2
5 0 RW Y GRP0_OV_DLTA1
4 0 RW Y GRP0_OV_DLTA0
3 0 RW Y GRP1_OV_DLTA3 Sets the PPM delta tolerance for the PPM counter lock check for group 1. Must also program channel register 0x67[6].
2 0 RW Y GRP1_OV_DLTA2
1 0 RW Y GRP1_OV_DLTA1
0 0 RW Y GRP1_OV_DLTA0
65 7:0 0 RW N RESERVED
66 7:0 0 RW N RESERVED
67 7:0 0x20 RW Y RESERVED
68 7:0 0 RW N RESERVED
69 7:5 0 RW N RESERVED
4 0 RW N CTLE_ADPT_FRC_EN This feature is reserved for future use.
3 1 RW Y HV_LCKMON_CNT_MS3
2 0 RW Y HV_LCKMON_CNT_MS2
1 1 RW Y HV_LCKMON_CNT_MS1
0 0 RW Y HV_LCKMON_CNT_MS0
6A 7 0 RW Y VEO_LCK_THRSH3 VEO threshold to meet before lock is established. The LSB step size is 4 counts of VEO.
6 0 RW Y VEO_LCK_THRSH2
5 1 RW Y VEO_LCK_THRSH1
4 0 RW Y VEO_LCK_THRSH0
3 0 RW Y HEO_LCK_THRSH3 HEO threshold to meet before lock is established. The LSB step size is 4 counts of VEO.
2 0 RW Y HEO_LCK_THRSH2
1 1 RW Y HEO_LCK_THRSH1
0 0 RW Y HEO_LCK_THRSH0
6B 7 0 RW Y FOM_A7 Alternate Figure of Merit variable A. Max value for this register is 128, do not use the MSB
6 1 RW Y FOM_A6
5 0 RW Y FOM_A5
4 0 RW Y FOM_A4
3 0 RW Y FOM_A3
2 0 RW Y FOM_A2
1 0 RW Y FOM_A1
0 0 RW Y FOM_A0
6C 7 0 RW Y FOM_B7 HEO adjustment for Alternate FoM, variable B
6 1 RW Y FOM_B6
5 0 RW Y FOM_B5
4 0 RW Y FOM_B4
3 0 RW Y FOM_B3
2 0 RW Y FOM_B2
1 0 RW Y FOM_B1
0 0 RW Y FOM_B0
6D 7 0 RW Y FOM_C7 VEO adjustment for Alternate FoM, variable C
6 1 RW Y FOM_C6
5 0 RW Y FOM_C5
4 0 RW Y FOM_C4
3 0 RW Y FOM_C3
2 0 RW Y FOM_C2
1 0 RW Y FOM_C1
0 0 RW Y FOM_C0
6E 7 0 RW Y EN_NEW_FOM_CTLE 1: CTLE adaption state machine will use the alternate FoM HEO_ALT = (HEO-B)*A*2 VEO_ALT = (VEO-C)*(1-A)*2
The values of A,B,C are set in channel register 0x6B, 0x6C, and 0x6D. The value of A is equal to the register value divided by 128.
The Alternate FoM = (HEOB)* A*2 + (VEO-C)*(1-A)*2
6 0 RW Y EN_NEW_FOM_DFE 1: DFE adaption state machine will use the alternate FoM HEO_ALT = (HEO-B)*A*2 VEO_ALT = (VEO-C)*(1-A)*2
The values of A,B,C are set in channel register 0x6B, 0x6C, and 0x6D. The value of A is equal to the register value divided by 128
The Alternate FoM = (HEOB)* A*2 + (VEO-C)*(1-A)*2
5:1 0 RW N RESERVED
0 0 RW N GET_HV_ST_FRC_EN This feature is reserved for future use.
6F 7:5 0 RW Y RESERVED
4:0 0 RW N RESERVED
70 7:4 0 RW N RESERVED
3 0 RW N RESERVED
2 0 RW Y EQ_LB_CNT2 CTLE look beyond count for adaption
1 1 RW Y EQ_LB_CNT1
0 1 RW Y EQ_LB_CNT0
71 7:6 0 RW N RESERVED
5 0 R N DFE_POL_1_OBS Primary observation point for DFE tap 1 polarity
4 0 R N DFE_WT1_OBS4 Primary observation point for DFE tap 1 weight
3 0 R N DFE_WT1_OBS3
2 0 R N DFE_WT1_OBS2
1 0 R N DFE_WT1_OBS1
0 0 R N DFE_WT1_OBS0
72 7:5 0 RW N RESERVED
4 0 R N DFE_POL_2_OBS Primary observation point for DFE tap 2 polarity
3 0 R N DFE_WT2_OBS3 Primary observation point for DFE tap 2 weight
2 0 R N DFE_WT2_OBS2
1 0 R N DFE_WT2_OBS1
0 0 R N DFE_WT2_OBS0
73 7:5 0 RW N RESERVED
4 0 R N DFE_POL_3_OBS Primary observation point for DFE tap 3 polarity
3 0 R N DFE_WT3_OBS3 Primary observation point for DFE tap 3 weight
2 0 R N DFE_WT3_OBS2
1 0 R N DFE_WT3_OBS1
0 0 R N DFE_WT3_OBS0
74 7:5 0 RW N RESERVED
4 0 R N DFE_POL_4_OBS Primary observation point for DFE tap 4 polarity
3 0 R N DFE_WT4_OBS3 Primary observation point for DFE tap 4 weight
2 0 R N DFE_WT4_OBS2
1 0 R N DFE_WT4_OBS1
0 0 R N DFE_WT4_OBS0
75 7:5 0 RW N RESERVED
4 0 R N DFE_POL_5_OBS Primary observation point for DFE tap 5 polarity
3 0 R N DFE_WT5_OBS3 Primary observation point for DFE tap 5 weight
2 0 R N DFE_WT5_OBS2
1 0 R N DFE_WT5_OBS1
0 0 R N DFE_WT5_OBS0