SNLS459A APRIL   2013  – October 2015 DS125RT410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 Signal Detect
      3. 7.3.3 CTLE
      4. 7.3.4 Clock and Data Recovery
      5. 7.3.5 Output Driver
      6. 7.3.6 Device Configuration
        1. 7.3.6.1 Rate and Subrate Setting
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Master Mode and SMBus Slave Mode
      2. 7.4.2 Address Lines <ADDR_[3:0]>
      3. 7.4.3 SDA and SDC
      4. 7.4.4 Standards-Based Modes
        1. 7.4.4.1 Ref_mode 3 Mode (Reference Clock Required)
        2. 7.4.4.2 False Lock Detector Setting
        3. 7.4.4.3 Reference Clock In
        4. 7.4.4.4 Reference Clock Out
        5. 7.4.4.5 Driver Output Voltage
        6. 7.4.4.6 Driver Output De-Emphasis
        7. 7.4.4.7 Driver Output Rise and Fall Time
        8. 7.4.4.8 INT
        9. 7.4.4.9 LOCK_3, LOCK_2, LOCK_1, and LOCK_0
    5. 7.5 Programming
      1. 7.5.1  SMBus Strap Observation
      2. 7.5.2  Device Revision and Device ID
      3. 7.5.3  Control/Shared Register Reset
      4. 7.5.4  Interrupt Channel Flag Bits
      5. 7.5.5  SMBus Master Mode Control Bits
      6. 7.5.6  Resetting Individual Channels of the Retimer
      7. 7.5.7  Interrupt Status
      8. 7.5.8  Overriding the CTLE Boost Setting
      9. 7.5.9  Overriding the VCO Search Values
      10. 7.5.10 Overriding the Output Multiplexer
      11. 7.5.11 Overriding the VCO Divider Selection
      12. 7.5.12 Using the PRBS Generator
      13. 7.5.13 Using the Internal Eye Opening Monitor
      14. 7.5.14 Enabling Slow Rise and Fall Time on the Output Driver
      15. 7.5.15 Inverting the Output Polarity
      16. 7.5.16 Overriding the Figure of Merit for Adaptation
      17. 7.5.17 Setting the Rate and Subrate for Lock Acquisition
      18. 7.5.18 Setting the Adaptation/Lock Mode
      19. 7.5.19 Initiating Adaptation
      20. 7.5.20 Setting the Reference Enable Mode
      21. 7.5.21 Overriding the CTLE Settings Used for CTLE Adaptation
      22. 7.5.22 Setting the Output Differential Voltage
      23. 7.5.23 Setting the Output De-Emphasis Setting
    6. 7.6 Register Maps
      1. 7.6.1 Register Information
      2. 7.6.2 Bit Fields in the Register Set
      3. 7.6.3 Writing to and Reading from the Control/Shared Registers
      4. 7.6.4 Channel Select Register
      5. 7.6.5 Reading to and Writing from the Channel Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS125RT410 is a 4-channel retimer that supports many different data rates and application spaces.

The following sections describe the typical use cases and common implementation practices.

8.2 Typical Application

Figure 6 shows a typical system implementation, where the DS125RT410 is used both on the backplane and port side.

DS125RT410 30161080A.gif Figure 6. Typical Application Diagram

8.2.1 Design Requirements

This section lists some critical areas for high speed printed circuit board design consideration and study.

  • Use 100-Ω differential impedance traces.
  • Back-drill connector vias and signal vias to minimize stub length.
  • Use reference plane vias to ensure a low inductance path for the return current.
  • Place AC-coupling capacitors for the transmitter links near the receiver for that channel.
  • The maximum body size for AC-coupling capacitors is 0402.

8.2.2 Detailed Design Procedure

To begin the design process, determine the following:

  • Maximum power draw for PCB regulator selection: for this calculation, use the maximum transient power supply current specified in the data sheet. The lock time for each channel is typically very short, so this power calculation should not be used for the thermal simulations of the PCB.
  • Maximum operational power for thermal calculations: for this calculation, use the Average Power Consumption value in Electrical Characteristics.
  • Select a reference clock frequency and routing scheme.
  • Plan out channel connectivity. Be sure to note any desired polarity inversion routing in the board schematics.
  • Ensure that each device has a unique SMBus address if the control bus is shared with other devices or components.
  • Use the IBIS-AMI model for simple channel simulations before PCB layout is complete.

8.2.3 Application Curves

Figure 7 shows a typical output eye diagram for the DS125RT410 operating at 12.5 Gbps with default VOD of 600 mVp-p and de-emphasis setting of –2 dB.

Figure 8 shows an example of TX de-emphasis for a DS125RT410 operating at 12.5 Gbps. In this example, the high speed output is configured for 600-mVp-p VOD and de-emphasis is set to –4.5 dB. An 8T pattern is used to evaluate the driver, which consists of 0xFF00.

Figure 9 shows a typical output eye diagram for the DS125RT410 operating at 10.3125 Gbps with default VOD of 600 mVp-p and de-emphasis setting of –2 dB.

Figure 10 shows an example of TX de-emphasis for a DS125RT410 operating at 10.3125 Gbps. In this example, the high speed output is configured for 600-mVp-p VOD and de-emphasis is set to –4.5 dB. An 8T pattern is used to evaluate the driver, which consists of 0xFF00.

DS125RT410 wvfrm01_DF410_DS_Tx_eye_12p5G_snls398.gif Figure 7. Typical Output Eye Diagram for the DS125RT410 Operating at 12.5 Gbps
DS125RT410 wvfrm03_DF410_DS_Tx_eye_10p3125G_snls398.gif Figure 9. Typical Output Eye Diagram for the DS125RT410 Operating at 10.3125 Gbps With Default VOD of 600 mVp-p and De-emphasis Setting of –2 dB
DS125RT410 wvfrm02_DF410_DS_Tx_8T_12p5G_snls398.gif Figure 8. Example of TX De-emphasis for a DS125RT410 Operating at 12.5 Gbps
DS125RT410 wvfrm04_DF410_DS_Tx_8T_10p3125G_snls398.gif Figure 10. Example of TX De-emphasis for a DS125RT410 Operating at 10.3125 Gbps