SNLS732 February   2023 DS160PR1601

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD and Latchup Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Control and Configuration Interface
      1. 7.3.1 Pin Configurations for Lanes
        1. 7.3.1.1 Five-Level Control Inputs
      2. 7.3.2 SMBUS/I2C Register Control Interface
      3. 7.3.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
    4. 7.4 Feature Description
      1. 7.4.1 Linear Equalization
      2. 7.4.2 Flat-Gain
      3. 7.4.3 Analog EyeScan
      4. 7.4.4 Receiver Detect State Machine
      5. 7.4.5 Integrated Capacitors
    5. 7.5 Device Functional Modes
      1. 7.5.1 Active PCIe Mode
      2. 7.5.2 Active Buffer Mode
      3. 7.5.3 Standby Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x16 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.3 Application Curves

The DS160PR1601 is a linear redriver that can be used to extend channel reach of a PCIe link. Normally, PCIe-compliant Tx and Rx are equipped with signal-conditioning functions and can handle channel losses of up to 28 dB at 16 Gbps (8 GHz) PCIe 4.0. With the DS160PR1601, the total channel loss between a PCIe root complex and an end point can be extended up to 42 dB (16 dB additional) at 8 GHz.

To demonstrate the reach extension capability of the DS160PR1601, two comparative setups are constructed. In first setup as shown in #X3590 there is no redriver in the PCIe 5.0 link. #FIG_L1S_HK3_BTB shows eye diagram at the end of the link using SigTest. In second setup as shown in #GUID-061CC0D4-53D5-4E4F-9D6B-47062873D590, the DS160PR1601 is inserted in the middle to extend link reach. #FIG_QSP_3K3_BTB shows SigTest eye diagram.

Figure 8-3 PCIe 4.0 Link Baseline Setup Without Redriver – Link Elements
Figure 8-5 PCIe 4.0 Link Setup with the DS160PR1601 – the Link Elements
GUID-20230201-SS0I-DMDS-QWH9-PFZCCWQGP37G-low.pngFigure 8-4 PCIe 4.0 link Baseline Setup Without Redriver – Eye Diagram Using SigTest
GUID-20230201-SS0I-W7CN-64LV-QXPF2TV7NDDS-low.pngFigure 8-6 PCIe 4.0 Link Setup with the DS160PR1601 – Eye Diagram Using SigTest

Table 8-1 summarizes the PCIe 4.0 links without and with the DS160PR1601. The illustration shows that redriver is capable of ≅16 dB (additional) reach extension at PCIe 4.0 speed with EQ = 15 and flat_gain = 101. Note: actual reach extension depends on various signal integrity factors. It is recommended to run signal intergrity simulations with all the components in the link to get any guidance.

Table 8-1 PCIe 4.0 Reach Extension Using the DS160PR1601
Setup Pre Channel Loss Post Channel Loss Total Loss Eye at BER 1E-12 SigTest Pass?
Baseline – no DUT — — ≅27 dB 29 ps, 48 mV Pass
With DUT (DS160PR1601) ≅25 dB ≅18 dB ≅43 dB 30 ps, 55 mV Pass