SNLS732 February   2023 DS160PR1601

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD and Latchup Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Control and Configuration Interface
      1. 7.3.1 Pin Configurations for Lanes
        1. 7.3.1.1 Five-Level Control Inputs
      2. 7.3.2 SMBUS/I2C Register Control Interface
      3. 7.3.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
    4. 7.4 Feature Description
      1. 7.4.1 Linear Equalization
      2. 7.4.2 Flat-Gain
      3. 7.4.3 Analog EyeScan
      4. 7.4.4 Receiver Detect State Machine
      5. 7.4.5 Integrated Capacitors
    5. 7.5 Device Functional Modes
      1. 7.5.1 Active PCIe Mode
      2. 7.5.2 Active Buffer Mode
      3. 7.5.3 Standby Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x16 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 High Speed Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Receiver
RLRX-DIFF Input differential return loss 50 MHz to 1.25 GHz -20 dB
1.25 GHz to 2.5 GHz -19 dB
2.5 GHz to 4.0 GHz -16 dB
4.0 GHz to 8.0 GHz -12 dB
RLRX-CM Input common-mode return loss 50 MHz to 2.5 GHz -15 dB
2.5 GHz to 8.0 GHz -15 dB
XTRX Receive-side pair-to-pair isolation Pair-to-pair isolation (SDD21) between two adjacent receiver pairs from 10 MHz to 8 GHz. -50 dB
Transmitter
VTX-AC-CM-PP Tx AC Peak-to-Peak Common Mode Voltage Measured with lowest EQ, flat_gain = 101 50 mVpp
VTX-RCV-DETECT Amount of Voltage change allowed during Receiver Detection Measured while Tx is sensing whether a low-impedance Receiver is present. No load is connected to the driver output 0 600 mV
RLTX-DIFF Output differential return loss 50 MHz to 1.25 GHz -19 dB
1.25 GHz to 2.5 GHz -17 dB
2.5 GHz to 4.0 GHz -12 dB
4.0 GHz to 8.0 GHz -10 dB
RLTX-CM Output Common-mode return loss 50 MHz to 2.5 GHz -14 dB
2.5 GHz to 8.0 GHz  -12 dB
XTTX Transmit-side pair-to-pair isolation Minimum pair-to-pair isolation (SDD21) between two adjacent transmitter pairs from 10 MHz to 8 GHz. -50 dB
CAC,TX AC coupling capacitors on transmit pins 220 nF
Device Datapath
TPLHD/PHLD Input-to-output latency (propagation delay) through a data channel For either Low-to-High or High-to-Low transition.  130 170 ps
LTX-SKEW Lane-to-Lane Output Skew Between any two lanes within a single transmitter.  24 ps
TRJ-DATA Additive Random Jitter with data Jitter through redriver minus the calibration trace. 16 Gbps PRBS15. 800 mVpp-diff input swing. 100 fs
TRJ-INTRINSIC Intrinsic additive Random Jitter with clock Jitter through redriver minus the calibration trace. 8 Ghz CK. 800 mVpp-diff input swing. 100 fs
JITTERTOTAL-DATA Additive Total Jitter with data Jitter through redriver minus the calibration trace. 16 Gbps PRBS15. 800 mVpp-diff input swing. 2.0 ps
JITTERTOTAL-INTRINSIC Intrinsic additive Total Jitter with clock Jitter through redriver minus the calibration trace. 8 Ghz CK. 800 mVpp-diff input swing. 1.3 ps
EQ-MIN8G EQ boost at min setting (EQ INDEX = 0) AC gain at 8 GHz relative to gain at 100 MHz.  1.7 dB
EQ-MAX8G EQ boost at max setting (EQ INDEX = 19) AC gain at 8 GHz relative to gain at 100 MHz.  16 dB
FLAT-GAINVAR Flat gain variation across PVT measured at DC Flat_gain = 000, 001, 011, 101 or 111, at minimum EQ setting. Max-Min for a single channel.  -1.0 1.0 dB
EQ-GAINVAR,8G EQ boost variation across PVT At 8 Ghz. Flat_gain = 101, maximum EQ setting. Max-Min for a single channel.  -1.5 1.5 dB
LINEARITY-DC Output DC Linearity Flat_gain = 101. 128T pattern at 2.5 Gbps. 1800 mVpp
LINEARITY-AC Output AC Linearity Flat_gain = 101. 1T pattern at 16 Gbps. 1000 mVpp