SNLS686 February   2021 DS160PR421

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x8 Lane Switching
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Pin-to-pin Passive versus Redriver Option
        4. 8.2.1.4 Application Curves
      2. 8.2.2 DisplayPort Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 High Speed Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Receiver
RLRX-DIFF Input differential return loss 50 MHz to 1.25 GHz -25 dB
1.25 GHz to 2.5 GHz  -22 dB
2.5 GHz to 4.0 GHz  -21 dB
4.0 GHz to 8.0 GHz  -14 dB
XTRX Receive-side pair-to-pair isolation Pair-to-pair isolation (SDD21) between two adjacent active receiver pairs from 10 MHz to 8 GHz.  -47 dB
Transmitter
VTX-AC-CM-PP Tx AC Peak-to-Peak Common Mode Voltage Measured with lowest EQ, GAIN = L3; PRBS-7, 16 Gbps, over at least 106 bits using a bandpass-Pass Filter from 30 Khz - 500 Mhz 50 mVpp
VTX-CM-DC-ACTIVE-IDLE-DELTA Absolute Delta of DC Common Mode Voltage during L0 and Electrical Idle VTX-CM-DC = |VOUTn+ + VOUTn–|/2, Measured by taking the absolute difference of VTX-CM-DC during PCIe state L0 and Electrical Idle 0 100 mV
VTX-CM-DC-LINE-DELTA Absolute Delta of DC Common Mode Voltage between VOUTn+ and VOUTn– during L0 Measured by taking the absolute difference of VOUTn+ and VOUTn– during PCIe state L0 10 mV
VTX-IDLE-DIFF-AC-p AC Electrical Idle Differential Output Voltage Measured by taking the absolute difference of VOUTn+ and VOUTn– during Electrical Idle, Measured with a band-pass filter consisting of two first-order filters. The High-Pass and Low-Pass -3-dB bandwidths are 10 kHz and 1.25 GHz, respectively - zero at input 0 10 mV
VTX-IDLE-DIFF-DC DC Electrical Idle Differential Output Voltage Measured by taking the absolute difference of VOUTn+ and VOUTn– during Electrical Idle, Measured with a first-order Low-Pass Filter with –3-dB bandwidth of 10 kHz 0 5 mV
VTX-RCV-DETECT Amount of Voltage change allowed during Receiver Detection Measured while Tx is sensing whether a low-impedance Receiver is present. No load is connected to the driver output 0 600 mV
RLTX-DIFF Output differential return loss 50 MHz to 1.25 GHz  -20 dB
1.25 GHz to 2.5 GHz  -18 dB
2.5 GHz to 4.0 GHz  -18 dB
4.0 GHz to 8.0 GHz  -16 dB
XTTX Transmit-side pair-to-pair isolation Minimum pair-to-pair isolation (SDD21) between two adjacent active transmitter pairs from 10 MHz to 8 GHz.  -48 dB
Device Datapath
TPLHD/PHLD Input-to-output latency (propagation delay) through a data channel For either Low-to-High or High-to-Low transition 80 110 ps
LTX-SKEW Lane-to-Lane Output Skew Between any two lanes within a single transmitter. -20 20 ps
TRJ-DATA Additive Random Jitter with data Difference between through redriver and baseline setup. 16Gbps PRBS15. Minimal input/output channels. Minimum EQ. 800 mVpp-diff input swing. 70 fs
TRJ-INTRINSIC Intrinsic additive Random Jitter with clock Difference between through redriver and baseline setup. 8 Ghz CK. Minimal input/output channels. Minimum EQ. 400 mVpp-diff input swing. 90 fs
JITTERTOTAL-DATA Additive Total Jitter with data Difference between through redriver and baseline setup. 16 Gbps PRBS15. Minimal input/output channels. Minimum EQ. 800 mVpp-diff input swing. 4 ps
JITTERTOTAL-INTRINSIC Intrinsic additive Total Jitter with clock Difference between through redriver and baseline setup. 8 Ghz CK. Minimal input/output channels. Minimum EQ. 800 mVpp-diff input swing. 1 ps
DCGAIN DC flat gain input to output Minimum EQ, GAIN = L0 -4.2 dB
Minimum EQ, GAIN = L1 -1.8 dB
Minimum EQ, GAIN = L2 0.25 dB
Minimum EQ, GAIN = L3 (Float) 2.0 dB
EQ-MAX8G EQ boost at max setting (EQ INDEX = 15) AC gain at 8 GHz relative to gain at 100 MHz.  17 dB
DCGAINVAR DC gain variation  GAIN = L2, minimum EQ setting. Max-Min.  -2.3 1.7 dB
EQGAINVAR EQ boost variation At 8 Ghz. GAIN1/0 = L2, maximum EQ setting. Max-Min.  -3.3 3.7 dB
LINDC Output DC Linearity GAIN = L3 (defauult). 128T pattern at 2.5 Gbps.  1000 mVpp
LINAC Output AC Linearity GAIN = L3 (default). 1T pattern at 16 Gbps.  750 mVpp