SNLS680 December   2020 DS160UP822

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat Gain
      3. 7.3.3 Cross Point
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
        3. 7.5.1.3 SMBus/I 2 C Master Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 UPI 2x2 Cross Point Mux for x24 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 DC Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power
POWERCH Active power per channel GAIN1/0 = L3 (default) 107 mW
GAIN1/0 = L0 99 mW
IACTIVE-8CH Device current consumption when all eight channels are active GAIN1/0 = L3 260 360 mA
ISTBY Device current consumption in standby power mode All channels disabled (PD1,0 = H) 30 45 mA
VREG Internal regulator output 2.5 V
Control IO (SDA, SCL, PD1, PD0, READ_EN_N, SEL1, SEL0 pins)
VIH High level input voltage SDA, SCL, PD1, PD0, READ_EN_N, SEL1, SEL0 pins 2.1 V
VIL Low level input voltage SDA, SCL, PD1, PD0, READ_EN_N, SEL1, SEL0 pins 1.08 V
VOH High level output voltage Rpull-up = 4.7 kΩ (SDA, SCL, ALL_DONE_N pins) 2.1 V
VOL Low level output voltage IOL = –4 mA (SDA, SCL, ALL_DONE_N pins) 0.4 V
IIH,SEL Input high leakage current for SEL pins VInput = VCC for SEL1, SEL0 pins 80 µA
IIH Input high leakage current VInput = VCC, (SCL, SDA, PD1, PD0, READ_EN_N pins) 10 µA
IIL Input low leakage current VInput = 0 V, (SCL, SDA, PD1, PD0, READ_EN_N, SEL1, SEL0 pins) -10 µA
IIH,FS Input high leakage current for fail safe input pins VInput = 3.6 V, VCC = 0 V, (SCL, SDA, , PD1, PD0, READ_EN_N, SEL1, SEL0 pins) 200 µA
CIN-CTRL Input capacitance SDA, SCL, PD1, PD0, READ_EN_N, SEL1, SEL0 pins 1.5 pF
4 Level IOs (MODE, GAIN0, GAIN1, EQ0_0, EQ1_0, EQ0_1, EQ1_1, RX_DET pins)
IIH_4L Input high leakage current, 4 level IOs VIN = 2.5 V 10 µA
IIL_4L Input low leakage current for all 4 level IOs except MODE. VIN = GND -10 µA
IIL_4L,MODE Input low leakage current for MODE pin VIN = GND -200 µA
Receiver
VRX-DC-CM RX DC common mode (CM) voltage Device is in active or standby state 2.5 V
ZRX-DC Rx DC single-ended impedance 50 Ω
ZRX-HIGH-IMP-DC-POS DC input CM input impedance   during Reset or power-down Inputs are at CM voltage 20 kΩ
Transmitter
ZTX-DIFF-DC DC differential Tx impedance Impedance of Tx during active signaling, VID,diff = 1Vpp 100 Ω
VTX-DC-CM Tx DC common mode Voltage 0.75 V
ITX-SHORT Tx Short circuit current Total current the Tx can supply when shorted to GND 90 mA