SNLS680 December   2020 DS160UP822

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat Gain
      3. 7.3.3 Cross Point
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
        3. 7.5.1.3 SMBus/I 2 C Master Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 UPI 2x2 Cross Point Mux for x24 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 High Speed Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Receiver
RLRX-DIFF Input differential return loss 50 MHz to 1.25 GHz -25 dB
1.25 GHz to 2.5 GHz -22 dB
2.5 GHz to 4.0 GHz -21 dB
4.0 GHz to 8.0 GHz -16 dB
XTRX Receive-side pair-to-pair isolation Pair-to-pair isolation (SDD21) between two adjacent receiver pairs from 10 MHz to 8 GHz. -47 dB
Transmitter
RLTX-DIFF Output differential return loss 50 MHz to 1.25 GHz -20 dB
1.25 GHz to 2.5 GHz -18 dB
2.5 GHz to 4.0 GHz -18 dB
4.0 GHz to 8.0 GHz -17 dB
XTTX Transmit-side pair-to-pair isolation Minimum pair-to-pair isolation (SDD21) between two adjacent transmitter pairs from 10 MHz to 8 GHz. -48 dB
Device Datapath
TPLHD/PHLD Input-to-output latency (propagation delay) through a data channel For either low-to-high or high-to-low transition.  90 120 ps
LTX-SKEW Lane-to-lane output skew Between any two lanes within a single transmitter.  -20 20 ps
TRJ-DATA Additive random jitter with data Jitter through redriver minus the calibration trace. 16Gbps PRBS15. Minimal input/output channels. Minimum EQ. 800 mVpp-diff input swing. 70 fs
TRJ-INTRINSIC Intrinsic additive random jitter with clock Jitter through redriver minus the calibration trace. 8 Ghz CK. Minimal input/output channels. Minimum EQ. 400 mVpp-diff input swing. 90 fs
JITTERTOTAL-DATA Additive total jitter with data Jitter through redriver minus the calibration trace. 16 Gbps PRBS15. Minimal input/output channels. Minimum EQ. 800 mVpp-diff input swing. 4 ps
JITTERTOTAL-INTRINSIC Intrinsic additive total jitter with clock Jitter through redriver minus the calibration trace. 8 Ghz CK. Minimal input/output channels. Minimum EQ. 800 mVpp-diff input swing. 1 ps
FLAT-GAIN Flat gain (DC and AC) input to output Minimum EQ, GAIN1/0=L0  -4.2 dB
Minimum EQ, GAIN1/0=L1  -1.8 dB
Minimum EQ, GAIN1/0=L2  0.25 dB
Minimum EQ, GAIN1/0=L3 (float, default)  2 dB
EQ-MAX8G EQ boost at max setting (EQ INDEX = 15) AC gain at 8 GHz relative to gain at 100 MHz. GAIN1/0=L3 (float, default).  18.0 dB
DCGAINVAR DC gain variation  GAIN1/0 = L2, minimum EQ setting. Max-Min.  -2.3 1.7 dB
EQGAINVAR EQ boost variation At 8 Ghz. GAIN1/0 = L2, maximum EQ setting. Max-Min.  -3.3 3.7 dB
LINDC Output DC linearity GAIN1/0 = L3 (float, default). 128T pattern at 2.5 Gbps. 1000 mVpp
LINAC Output AC linearity GAIN1/0 = L3 (float, default). 1T pattern at 16 Gbps.  750 mVpp