SNLS590C August   2018  – June 2021 DS250DF230

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  Signal Detect
      3. 8.3.3  Continuous Time Linear Equalizer (CTLE)
      4. 8.3.4  Variable Gain Amplifier (VGA)
      5. 8.3.5  Cross-Point Switch
      6. 8.3.6  Decision Feedback Equalizer (DFE)
      7. 8.3.7  Clock and Data Recovery (CDR)
        1. 8.3.7.1 CDR Bypass (Raw) Mode
        2. 8.3.7.2 CDR Fast Lock Mode
      8. 8.3.8  Calibration Clock
      9. 8.3.9  Differential Driver With FIR Filter
        1. 8.3.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
        2. 8.3.9.2 Output Driver Polarity Inversion
        3. 8.3.9.3 Slow Slew Rate
      10. 8.3.10 Debug Features
        1. 8.3.10.1 Pattern Generator
        2. 8.3.10.2 Pattern Checker
        3. 8.3.10.3 Eye-Opening Monitor
      11. 8.3.11 Interrupt Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Front-Port Jitter Cleaning Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Cable Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Backplane and Mid-Plane Applications
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
  13. 13Electrostatic Discharge Caution
  14. 14Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2 SMBus Master Mode

SMBus master mode allows the DS250DF230 to program itself by reading directly from an external EEPROM. When using the SMBus master mode, the DS250DF230 will read directly from specific location in the external EEPROM. When designing a system for using the external EEPROM, the user must follow these specific guidelines:

  • Maximum EEPROM size is 2048 Bytes
  • Minimum EEPROM size for a single DS250DF230 with individual channel configuration is 161 Bytes (3 base header bytes + 12 address map bytes + 2 × 72 channel register bytes + 2 share register bytes; bytes are defined to be 8-bits)
  • Set ENSMB = Float, for SMBus master mode
  • The external EEPROM device address byte must be 0xA0
  • The external EEPROM device must support 400kHz operation at 2.5-V or 3.3-V supply
  • THR pin is pulled low by 1 kΩ to GND, so that DS250DF230 is working under 2.5-V/3.3-V SMBus interface mode
  • Set the SMBus address of the DS250DF230 by configuring the ADDR0 and ADDR1 pins

When loading multiple DS250DF230 devices from the same EEPROM, use these guidelines to configure the devices:

  • Configure the SMBus addresses for each DS250DF230 to be sequential. The first device in the sequence must have an address of 0x30
  • Daisy chain READ_EN_N and ALL_DONE_N from one device to the next device in the sequence so that they do not compete for the EEPROM at the same time.
  • If all of the DS250DF230 devices share the same EEPROM channel and share register settings, configure the common channel bit in the base header to 1. With common channel configuration enabled, each DS250DF230 device will configure all 2 channels with the same settings.

When loading a single DS250DF230 from an EEPROM, use these guidelines to configure the device:

  • Set the common channel bit to 0 to allow for individual channel configuration, or set the common channel bit to 1 to load the same configuration settings to all channels.
  • When configuring individual channels, a 512, 1024 or 2048 Byte EEPROM must be used.
  • If there are more than three DS250DF230 devices on a PCB that require individual channel configuration, then each device must have its own EEPROM.