SNLS513C December   2015  – October 2019 DS250DF810

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, Retimer Jitter Specifications
    7. 7.7  Timing Requirements, Retimer Specifications
    8. 7.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 7.9  Recommended SMBus Switching Characteristics (Slave Mode)
    10. 7.10 Recommended SMBus Switching Characteristics (Master Mode)
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  AC-Coupled Receiver and Transmitter
      3. 8.3.3  Signal Detect
      4. 8.3.4  Continuous Time Linear Equalizer (CTLE)
      5. 8.3.5  Variable Gain Amplifier (VGA)
      6. 8.3.6  Cross-Point Switch
      7. 8.3.7  Decision Feedback Equalizer (DFE)
      8. 8.3.8  Clock and Data Recovery (CDR)
      9. 8.3.9  Calibration Clock
      10. 8.3.10 Differential Driver with FIR Filter
      11. 8.3.11 Setting the Output VOD
      12. 8.3.12 Output Driver Polarity Inversion
      13. 8.3.13 Debug Features
        1. 8.3.13.1 Pattern Generator
        2. 8.3.13.2 Pattern Checker
        3. 8.3.13.3 Eye Opening Monitor
      14. 8.3.14 Interrupt Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Backplane and Mid-Plane Applications
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6 Register Maps

Table 7. Global Registers

ADDRESS
(HEX)		 BITS DEFAULT
VALUE
(HEX)		 MODE EEPROM FIELD NAME DESCRIPTION
EF 7 0 R N SPARE
6 0 R N SPARE
5 0 R N SPARE
4 0 R N SPARE
3 1 R N CHAN_CONFIG_ID[3]
2 1 R N CHAN_CONFIG_ID[2]
1 0 R N CHAN_CONFIG_ID[1]
0 0 R N CHAN_CONFIG_ID[0]
F0 7 0 R N VERSION[7]
6 0 R N VERSION[6]
5 1 R N VERSION[5]
4 1 R N VERSION[4]
3 0 R N VERSION[3]
2 0 R N VERSION[2]
1 1 R N VERSION[1]
0 0 R N VERSION[0]
F1 7 0 R N DEVICE_ID[7] Full device ID
6 0 R N DEVICE_ID[6]
5 0 R N DEVICE_ID[5]
4 1 R N DEVICE_ID[4]
3 0 R N DEVICE_ID[3]
2 0 R N DEVICE_ID[2]
1 0 R N DEVICE_ID[1]
0 0 R N DEVICE_ID[0]
F3 7 0 R N CHAN_VERSION[3] Digital Channel Version
6 0 R N CHAN_VERSION[2]
5 0 R N CHAN_VERSION[1]
4 0 R N CHAN_VERSION[0]
3 0 R N SHARE_VERSION[3] Digital Share Version
2 0 R N SHARE_VERSION[2]
1 0 R N SHARE_VERSION[1]
0 0 R N SHARE_VERSION[0]
FB 7 0 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 0 RW N RESERVED
2 1 RW N RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
FC 7 0 RW N EN_CH7 Select channel 7
6 0 RW N EN_CH6 Select channel 6
5 0 RW N EN_CH5 Select channel 5
4 0 RW N EN_CH4 Select channel 4
3 0 RW N EN_CH3 Select channel 3
2 0 RW N EN_CH2 Select channel 2
1 0 RW N EN_CH1 Select channel 1
0 0 RW N EN_CH0 Select channel 0
FD 7 0 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 0 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
FE 7 0 R N VENDOR_ID[7] TI vendor ID
6 0 R N VENDOR_ID[6]
5 0 R N VENDOR_ID[5]
4 0 R N VENDOR_ID[4]
3 0 R N VENDOR_ID[3]
2 0 R N VENDOR_ID[2]
1 1 R N VENDOR_ID[1]
0 1 R N VENDOR_ID[0]
FF 7 0 RW N RESERVED
6 0 RW N RESERVED
5 1 RW N EN_SHARE_Q1 Select shared registers for quad 1
4 0 RW N EN_SHARE_Q0 Select shared registers for quad 0
3 0 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N WRITE_ALL_CH Allows customer to write to all channels as if they are the same, but only allows read back from the channel specified in 0xFC and 0xFD.

Note: en_ch_SMB must be = 1 or else this function is invalid.
0 0 RW N EN_CH_SMB 1: Enables SMBUS access to the channels specified in register 0xFC
0: The shared registers are selected, see 0xFF[5:4]

Table 8. Shared Registers

ADDRESS
(HEX)		 BITS DEFAULT
VALUE
(HEX)		 MODE EEPROM FIELD
NAME		 DESCRIPTION
0 7 1 R N SMBus_Addr3 SMBus Address
6 1 R N SMBus_Addr2 Strapped 7-bit addres is 0x18 + SMBus_Addr[3:0]
5 0 R N SMBus_Addr1
4 0 R N SMBus_Addr0
3:0 0 RESERVED
1 7 1 R N RESERVED
6 0 R N RESERVED
5 1 R N RESERVED
4 1 R N RESERVED
3 0 R N RESERVED
2 0 R N RESERVED
1 0 R N RESERVED
0 1 R N RESERVED
2 7:0 0 RW N RESERVED
3 7:0 0 RW N RESERVED
4 7 0 RW N RESERVED
6 0 RW N RST_SMB_REGS 1: Resets share registers.
5 0 RWSC N RST_SMB_MAS 1: Reset for SMBus Master Mode
4 0 RW N rc_eeprm_rd 1: Force EEPROM Configuration
3 1 RW Y RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 1 RW N RESERVED
5 7 0 RW N disab_eeprm_cfg Disable Master Mode EEPROM Configuration
6:5 0 RW N RESERVED
4 1 R N EEPROM_READ_DONE This bit is set to 1 when read from EEPROM is done
3 0 RW N RESERVED
2 0 RW Y RESERVED
1 0 RW Y RESERVED
0 1 RW Y RESERVED
6 7:0 0 RW N RESERVED
8 7 0 R N RESERVED
6 0 R N RESERVED
5 0 R N RESERVED
4 0 R N RESERVED
3 0 R N int_q0c3 Interrupt from channel3 of quad0
2 0 R N int_q0c2 Interrupt from channel2 of quad0
1 0 R N int_q0c1 Interrupt from channel1 of quad0
0 0 R N int_q0c0 Interrupt from channel0 of quad0
A 7:1 0 R Y RESERVED
0 0 RW Y dis_refclk_out 1: Disable REFCLK_OUT (high-Z)
0: Enable REFCLK_OUT
B 7 0 RW N RESERVED
6 0 R N refclk_det High level when ref_clk has been detected
5 0 RW N RESERVED
4 0 RW N RESERVED
3 0 RW N mr_refclk_det_dis
2 0 RW N RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
C 7:0 0 RW N RESERVED
D 7:0 0 R N RESERVED
E 7:2 0 RW N RESERVED
1:0 0 R N RESERVED
F 7:0 0 RW N RESERVED
10 7 1 RW N RESERVED
6 1 RW N RESERVED
5 1 RW N RESERVED
4 1 RW N RESERVED
3 1 RW Y RESERVED
2 1 RW Y RESERVED
1 1 RW Y RESERVED
0 1 RW Y RESERVED
11 7 0 R N eecfg_cmplt 11: Not valid 10: EEPROM load completed successfully
01: EEPROM load failed after 64 attempts
00: EEPROM load in progress
6 0 R N eecfg_fail
5 0 R N eecfg_atmpt[5] Number of attempts made to load EEPROM image
4 0 R N eecfg_atmpt[4]
3 0 R N eecfg_atmpt[3]
2 0 R N eecfg_atmpt[2]
1 0 R N eecfg_atmpt[1]
0 0 R N eecfg_atmpt[0]
12 7 1 RW N reg_i2c_fast 1: EEPROM load uses Fast I2C Mode (400 kHz)
0: EEPROM load uses Standard I2C Mode (100 kHz)
6 0 RW N RESERVED
5 0 RW N RESERVED
4 1 RW N RESERVED
3 0 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 1 RW N RESERVED

Table 9. Channel Select Global Register Definition

ADDRESS
(HEX)		 BITS DESCRIPTION
0xFC 7 Select register set for channel 7
6 Select register set for channel 6
5 Select register set for channel 5
4 Select register set for channel 4
3 Select register set for channel 3
2 Select register set for channel 2
1 Select register set for channel 1
0 Select register set for channel 0

Table 10. Device/Vendor ID Global Register Definition

ADDRESS
(HEX)		 BITS DESCRIPTION
0xF0 TI Device ID. Contains 0x32.
0xF1 TI Device ID. Contains 0x10.
0xF3 TI Device ID. Contains 0x00.
0xFE TI Vendor ID. Read-only register. Contains value 0x03.

Table 11. Register Page Select Definition

ADDRESS
(HEX)		 BITS DESCRIPTION
0xFF 5 1: Selects shared registers for channels 4 -7
0: Normal operation
4 1: Selects shared registers for channels 0-3
0: Normal operation
1 1: Broadcast write to all channels, 0xFF[0] must be set to 1. Select a single channel in 0xFC.
0: Normal operation, select channel register as defined in 0xFC.
0 1: Select Channel Registers
0: Select Share Registers

Table 12. Channel Registers, 0 to 39

ADDRESS
(HEX)		 BITS DEFAULT
VALUE
(HEX)		 MODE EEPROM FIELD NAME DESCRIPTION
0 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RST_CORE 1: Reset the 10M core clock domain. This is the main clock domain for all the state machines
0: Normal operation
2 0 RW N RST_REGS 1: Reset channel registers to power-up defaults.
0: Normal operation
1 0 RW N RST_VCO 1: Resets the CDR S2P clock domain, includes PPM counter, EOM counter.
0: Normal operation
0 0 RW N RST_REFCLK 1: Resets the 25MHz reference clock domain, includes PPM counter. Does not work if 25MHz clock is not present.
0: Normal operation
1 7 0 R N sigdet Raw Signal Detect observation
6 0 R N pol_inv_det Indicates PRBS checker detected polarity inversion in the locked data sequence.
5 0 R N CDR_LOCK_LOSS_INT 1: Indicates loss of CDR lock after having acquired it. Bit clears on read. Feature must be enabled with reg_31[1]
4 0 R N prbs_seq_det[3] Indicates the pattern detected on the input serial stream
0xxx: No detect
1000: 7 bits PRBS sequence
1001: 9 bits PRBS sequence
1010: 11 bits PRBS sequence
1011: 15 bits PRBS sequence
1100: 23 bits PRBS sequence
1101: 31 bits PRBS sequence
1110: 58 bits PRBS sequence
1111: 63 bits PRBS sequence
3 0 R N prbs_seq_det[2]
2 0 R N prbs_seq_det[1]
1 0 R N prbs_seq_det[0]
0 0 R N SIG_DET_LOSS_INT Loss of signal indicator, set once signal is acquired and then lost. Clears on read. Feature must be enabled with reg_31[0]
2 7 0 R N CDR_STATUS[7] "This register is used to read the status of internal signal.
Select what is observable on this bus using Reg_0x0C[7:4]"
6 0 R N CDR_STATUS[6]
5 0 R N CDR_STATUS[5]
4 0 R N CDR_STATUS[4]
3 0 R N CDR_STATUS[3]
2 0 R N CDR_STATUS[2]
1 0 R N CDR_STATUS[1]
0 0 R N CDR_STATUS[0]
3 7 0 RW Y EQ_BST0[1] This register can be used to force an EQ boost setting if used in conjunction with channel register 0x2D[3].
6 0 RW Y EQ_BST0[0]
5 0 RW Y EQ_BST1[1]
4 0 RW Y EQ_BST1[0]
3 0 RW Y EQ_BST2[1]
2 0 RW Y EQ_BST2[0]
1 0 RW Y EQ_BST3[1]
0 0 RW Y EQ_BST3[0]
4 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
5 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
6 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
7 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
8 7 0 RW Y RESERVED RESERVED
6 1 RW Y RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 0 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 1 RW Y RESERVED RESERVED
9 7 0 RW Y REG_VCO_CAP_OV Enable bit to override cap_cnt with value in register and 0B[4:0]
6 0 RW Y REG_SET_CP_LVL_LPF_OV Enable bit to override lpf_dac_val with value in register 1F[4:0]
5 0 RW Y REG_BYPASS_PFD_OV Enable bit to override sel_retimedD_loopthru and sel_rawD_loopthru with values in reg1E[7:5]
4 0 RW Y REG_EN_FD_PD_VCO_PDIQ_OV Enable bit to override en_fd, pd_pd, pd_vco, pd_pdiq with reg1E[0], reg1E[2], reg1C[0], reg1C[1]
3 0 RW Y REG_EN_PD_CP_OV Enable bit to override pd_fd_cp and pd_pd_cp with value in register 1B[1:0]
2 0 RW Y REG_DIVSEL_OV Enable bit to override divsel with value in register 18[6:4]
1 0 RW Y RESERVED RESERVED
0 0 RW Y REG_PFD_LOCK_MODE_SM Enable fd in lock state
A 7 0 RW Y RESERVED RESERVED
6 0 RW Y REG_EN_IDAC_PD_CP_OV
AND_REG_EN_IDAC_FD_CP_OV		 Enable bit to override phase detector charge pump settings with reg1C[7:5]
Enable bit to override frequency detector charge pump settings with reg1C[4:2]"
5 0 RW Y REG_DAC_LPF_HIGH_PHASE_OV_AND_REG_DAC_LPF_LOW_PHASE_OV Enable bit to loop filter comparator trip voltages with reg16[7:0]
4 0 RW Y RESERVED RESERVED
3 0 RW N REG_CDR_RESET_OV Enable CDR Reset override with reg0A[2]
2 0 RW N REG_CDR_RESET_SM CDR Reset override bit
1 0 RW N REG_CDR_LOCK_OV Enable CDR lock signal override with reg0A[0]
0 0 RW N REG_CDR_LOCK CDR lock signal override bit
B 7 0 RW Y RESERVED RESERVED
6 1 RW Y RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 0 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 1 RW Y RESERVED RESERVED
C 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
D 7 1 RW N DES_PD "1: De-serializer (for PRBS checker) is powered down
0: De-serializer (for PRBS checker) is enabled"
6 0 RW N RESERVED RESERVED
5 0 RW Y RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 0 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
E 7 1 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 1 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 1 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
F 7 0 RW N RESERVED RESERVED
6 1 RW N RESERVED RESERVED
5 1 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 1 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
10 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
11 7 0 RW Y EOM_SEL_VRANGE[1] Manually set the EOM vertical range, used with channel register 0x2C[6]:
00: ±100 mV
01: ±200 mV
10: ±300 mV
11: ±400 mV
6 0 RW Y EOM_SEL_VRANGE[0]
5 1 RW Y EOM_PD 1: Normal operation
4 0 RW N RESERVED
3 0 RW Y DFE_TAP2_POL Bit forces DFE tap 2 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
2 0 RW Y DFE_TAP3_POL Bit forces DFE tap 3 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
1 0 RW Y DFE_TAP4_POL Bit forces DFE tap 4 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
0 0 RW Y DFE_TAP5_POL Bit forces DFE tap 5 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
12 7 1 RW Y DFE_TAP1_POL Bit forces DFE tap 1 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
6 0 RW N RESERVED
5 0 RW Y RESERVED
4 0 RW Y DFE_WT1[4] Bits force DFE tap 1 weight. Manual DFE operation required to take effect by setting 0x15[7]=1.
3 0 RW Y DFE_WT1[3]
2 0 RW Y DFE_WT1[2]
1 1 RW Y DFE_WT1[1]
0 1 RW Y DFE_WT1[0]
13 7 1 RW N eq_PD_PeakDetect
6 0 RW Y eq_PD_SD
5 1 RW Y eq_hi_gain
4 1 RW Y eq_en_dc_off
3 0 RW Y RESERVED
2 0 RW Y eq_limit_en 1: Configures the final stage of the equalizer to be a limiting stage.
0: Normal operation, final stage of the equalizer is configured to be a linear stage.
1 0 RW Y RESERVED
0 0 RW Y RESERVED
14 7 0 RW Y EQ_SD_PRESET 1: Forces signal detect HIGH, and force enables the channel. Should not be set if bit 6 is set.
0: Normal Operation.
6 0 RW Y EQ_SD_RESET 1: Forces signal detect LOW and force disables the channel. Should not be set if bit 7 is set.
0: Normal Operation.
5 0 RW Y EQ_REFA_SEL1 Controls the signal detect assert levels.
4 0 RW Y EQ_REFA_SEL0
3 0 RW Y EQ_REFD_SEL1 Controls the signal detect de-assert levels.
2 1 RW Y EQ_REFD_SEL0
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
15 7 0 RW Y DFE_FORCE_EN 1: Enables manual DFE tap settings
0: Normal operation
6 0 RW N RESERVED
5 0 RW N RESERVED
4 1 RW Y RESERVED
3 0 RW Y DRV_PD 1: Powers down the high speed driver
0: Normal operation
2 0 RW Y RESERVED
1 0 RW Y RESERVED
0 0 RW Y RESERVED
16 7 0 RW Y RESERVED RESERVED
6 1 RW Y RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 1 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
17 7 0 RW Y RESERVED RESERVED
6 0 RW Y RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 0 RW Y RESERVED RESERVED
2 1 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
18 7 0 RW N RESERVED
6 1 RW Y PDIQ_SEL_DIV2 These bits will force the divider setting if 0x09[2] is set.
000: Divide by 1
001: Divide by 2
010: Divide by 4
011: Divide by 8
100: Divide by 16
All other values are reserved.
5 0 RW Y PDIQ_SEL_DIV1
4 0 RW Y PDIQ_SEL_DIV0
3 0 RW N RESERVED
2 0 RW Y RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
19 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 0 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 0 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
1A 7 0 RW Y RESERVED RESERVED
6 1 RW Y RESERVED RESERVED
5 0 RW Y RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 1 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
1B 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 1 RW Y CP_EN_CP_PD 1: Normal operation, phase detector charge pump enabled
0 1 RW Y CP_EN_CP_FD 1: Normal operation, frequency detector charge pump enabled
1C 7 1 RW Y EN_IDAC_PD_CP2 Phase detector charge pump setting. Override bit required for these bits to take effect
6 0 RW Y EN_IDAC_PD_CP1
5 0 RW Y EN_IDAC_PD_CP0
4 1 RW Y EN_IDAC_FD_CP2 Frequency detector charge pump setting. Override bit required for these bits to take effect
3 0 RW Y EN_IDAC_FD_CP1
2 0 RW Y EN_IDAC_FD_CP0
1 0 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
1D 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
1E 7 1 RW Y PFD_SEL_DATA_MUX2 For these values to take effect, register 0x09[5] must be set to 1.
000: Raw Data*
001: Retimed Data
100: Pattern Generator
111: Mute
All other values are reserved.
6 1 RW Y PFD_SEL_DATA_MUX1
5 1 RW Y PFD_SEL_DATA_MUX0
4 0 RW N SER_EN 1: Enable PRBS Generator
3 1 RW Y DFE_PD This bit must be cleared for the DFE to be functional in any adapt mode.
0: DFE enabled
1: DFE disabled
2 0 RW Y PFD_PD_PD PFD phase detector power down override
1 0 RW Y EN_PARTIAL_DFE 0: (Default) Disable DFE taps 3-5.
1: Enable DFE taps 3-5. DFE_PD must also be set to 0.
0 1 RW Y PFD_EN_FD PFD enable frequency detector override
1F 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 1 RW Y MR_LPF_AUTO_ADJST_EN "1: Allow LPF to tune to optimum value during fast-cap search routine
0: Otherwise LPF value is determined by the Reg_0x9D"
2 0 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 1 RW Y RESERVED RESERVED
20 7 0 RW Y DFE_WT5[3] Bits force DFE tap 5 weight, manual DFE operation required to take effect by setting 0x15[7]=1.
6 0 RW Y DFE_WT5[2]
5 0 RW Y DFE_WT5[1]
4 0 RW Y DFE_WT5[0]
3 0 RW Y DFE_WT4[3] Bits force DFE tap 4 weight, manual DFE operation required to take effect by setting 0x15[7]=1.
2 0 RW Y DFE_WT4[2]
1 0 RW Y DFE_WT4[1]
0 0 RW Y DFE_WT4[0]
21 7 0 RW Y DFE_WT3[3] Bits force DFE tap 3 weight, manual DFE operation required to take effect by setting 0x15[7]=1.
6 0 RW Y DFE_WT3[2]
5 0 RW Y DFE_WT3[1]
4 0 RW Y DFE_WT3[0]
3 0 RW Y DFE_WT2[3] Bits force DFE tap 2 weight, manual DFE operation required to take effect by setting 0x15[7]=1.
2 0 RW Y DFE_WT2[2]
1 0 RW Y DFE_WT2[1]
0 0 RW Y DFE_WT2[0]
22 7 0 RW N EOM_OV "1: Override enable for EOM manual control
0: Normal operation"
6 0 RW N EOM_SEL_RATE_OV "1: Override enable for EOM rate selection
0: Normal operation"
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
23 7 0 RW N EOM_GET_HEO_VEO_OV "1: Override enable for manual control of the HEO/VEO trigger
0: Normal operation"
6 1 RW Y DFE_OV 1: Normal operation; DFE must be enabled in Reg_0x1E[3]
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
24 7 0 RW N FAST_EOM 1: Enables fast EOM for full eye capture. In this mode the phase DAC and voltage DAC or the EOM are automatically incremented through a 64 x 64 matrix. Values for each point are stored in Reg_0x25 and Reg_0x26.
0: Normal operation
6 0 R N DFE_EQ_ERROR_NO_LOCK DFE/CTLE SM quit due to loss of lock
5 0 R N GET_HEO_VEO_ERROR_NO_HITS get_heo_veo sees no hits at zero crossing
4 0 R N GET_HEO_VEO_ERROR_NO_OPENING get_heo_veo cannot see a vertical eye opening
3 0 RW N RESERVED RESERVED
2 0 RWSC N DFE_ADAPT 1: Manually start DFE adaption (self-clearing)
0: Normal operation
1 0 R N EOM_GET_HEO_VEO 1: Manually triggers HEO/VEO measurement; feature must be enabled with Reg_0x23[7]; the HEO/VEO values are read from Reg_0x27, Reg_0x28
0 0 RWSC N EOM_START Starts EOM counter, self-clearing
25 7 0 R N EOM_COUNT15 MSBs of EOM counter
6 0 R N EOM_COUNT14
5 0 R N EOM_COUNT13
4 0 R N EOM_COUNT12
3 0 R N EOM_COUNT11
2 0 R N EOM_COUNT10
1 0 R N EOM_COUNT9
0 0 R N EOM_COUNT8
26 7 0 R N EOM_COUNT7 LSBs of EOM counter
6 0 R N EOM_COUNT6
5 0 R N EOM_COUNT5
4 0 R N EOM_COUNT4
3 0 R N EOM_COUNT3
2 0 R N EOM_COUNT2
1 0 R N EOM_COUNT1
0 0 R N EOM_COUNT0
27 7 0 R N HEO7 HEO value, requires CDR to be locked for valid measurement
6 0 R N HEO6
5 0 R N HEO5
4 0 R N HEO4
3 0 R N HEO3
2 0 R N HEO2
1 0 R N HEO1
0 0 R N HEO0
28 7 0 R N VEO7 VEO value, requires CDR to be locked for valid measurement
6 0 R N VEO6
5 0 R N VEO5
4 0 R N VEO4
3 0 R N VEO3
2 0 R N VEO2
1 0 R N VEO1
0 0 R N VEO0
29 7 0 RW N RESERVED RESERVED
6 0 R N EOM_VRANGE_SETTING[1] "Read the currently set Eye Monitor Voltage Range:
11 - +/-400mV
10 - +/- 300mV
01 - +/- 200mV
00 - +/- 100mV"
5 0 R N EOM_VRANGE_SETTING[0]
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 R N VEO[8] VEO MSB value
0 0 R N HEO[8] HEO MSB value
2A 7 0 RW Y EOM_TIMER_THR[3] The value of eom_timer_thr[7:0] controls the amount of time the Eye Monitor samples each point in the eye for. The total counter bit width is 16b, this register representing the upper 8b. Therefore, the count value is equal to {eom_timer_thr[7:0],8'h0}. The counter counts in 32b words. Therefore, the total number of bits counted is 32 times this value.
6 1 RW Y EOM_TIMER_THR[2]
5 0 RW Y EOM_TIMER_THR[1]
4 1 RW Y EOM_TIMER_THR[0]
3 1 RW Y VEO_MIN_REQ_HITS[3] Whenever the Eye Monitor is used to measure HEO and VEO, the data is sampled for some number of bits, set by Reg_0x2A[7:3]. This register sets the number of hits within that sample size that is required before the EOM will indicate a hit has occurred. This filtering only affects the VEO measurement.
2 0 RW Y VEO_MIN_REQ_HITS[2]
1 1 RW Y VEO_MIN_REQ_HITS[1]
0 0 RW Y VEO_MIN_REQ_HITS[0]
2B 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW Y RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 1 RW Y EOM_MIN_REQ_HITS[3] Whenever the Eye Monitor is used to measure HEO and VEO, the data is sampled for some number of bits, set by Reg_0x2A[7:3]. This register sets the number of hits within that sample size that is required before the EOM will indicate a hit has occured. This filtering only affects the HEO measurement.
2 0 RW Y EOM_MIN_REQ_HITS[2]
1 1 RW Y EOM_MIN_REQ_HITS[1]
0 0 RW Y EOM_MIN_REQ_HITS[0]
2C 7 1 RW N reload_dfe_taps Causes DFE taps to load from last adapted values
6 1 RW Y VEO_SCALE Scale VEO based on EOM vrange
5 1 RW Y DFE_SM_FOM1 This register defines the Figure of Merit used when adapting the DFE:
00: not valid
01: SM uses only HEO
10: SM uses only VEO
11: SM uses both HEO and VEO
Additionally, if Register 0x6E[6] is set to '1', the Alternate FOM is used. This bit takes precedence over DFE_SM_FOM
4 1 RW Y DFE_SM_FOM0
3 0 RW Y DFE_ADAPT_COUNTER3 DFE look-beyond count.
2 1 RW Y DFE_ADAPT_COUNTER2
1 1 RW Y DFE_ADAPT_COUNTER1
0 0 RW Y DFE_ADAPT_COUNTER0
2D 7 0 RW Y RESERVED RESERVED
6 0 RW Y RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 0 RW Y REG_EQ_BST_OV Allow override control of the EQ setting by writing to Reg_0x03
2 0 RW Y RESERVED RESERVED
1 0 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
2E 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 R N EQ_BST3_2_TO_ANALOG Read-back of eq_BST3[2] going to analog
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N PRBS_PATTERN_SEL[2] MSB for the PRBS_PATTERN_SEL field. Lower bits are found on register 0x30[1:0]. Refer to the register 0x30 description on this table.
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
2F 7 0 RW Y RESERVED RESERVED
6 1 RW Y RATE[2] Configure PPM register and divider for a standard data rate. Refer to Programming Guide.
5 0 RW Y RATE[1] Configure PPM register and divider for a standard data rate. Refer to Programming Guide.
4 1 RW Y RATE[0] Configure PPM register and divider for a standard data rate. Refer to Programming Guide.
3 0 RW Y INDEX_OV If this bit is 1, then Reg_0x39 is to be used as 4-bit index to the [15:0] array of EQ settings. The EQ setting at that index is loaded to the EQ boost registers going to the analog and is used as the starting point for adaption.
2 1 RW Y EN_PPM_CHECK Enable the PPM to be used as a qualifier when performing Lock Detect
1 0 RW Y RESERVED RESERVED
0 0 RWSC N CTLE_ADAPT Starts CTLE adaptation, self-clearing
30 7 0 RW N FREEZE_PPM_CNT Freeze the PPM counter to allow safe read asynchronously
6 0 RW Y EQ_SEARCH_OV_EN Enables the EQ 'search" bit to be forced by Reg_0x13[2]
5 0 RW N EN_PATT_INV Enable automatic pattern inversion of successive 16 bit words when using the "Fixed Pattern" generator option.
4 0 RW N RELOAD_PRBS_CHKR Force reload of seed into PRBS checker LFSR without holding the checker in reset.
3 0 RW N PRBS_EN_DIG_CLK This bit enables the clock to operate the PRBS generator and/or the PRBS checher. Toggling this bit is the primary method to reset the PRBS pattern generator and PRBS checker.
2 0 RW N PRBS_PROGPATT_EN "Enable a fixed data pattern output. Requires that serializer is enabled with Reg_0x1E[4]. PRBS generator and checker should be disabled, Reg_0x30[3]. The fixed data pattern is set by Reg_0x7C and Reg_0x97. Enable inversion of the pattern every 16 bits with Reg_0x30[5]".
1 0 RW N PRBS_PATTERN_SEL[1] "Selects the pattern output when using the PRBS generator. Requires the pattern generator to be configured properly. The MSB for the PRBS_PATTERN_SEL field is in Reg_0x2E[2].
Use Reg_0x30[3] to enable the PRBS generator.
000: 2^7-1 bits PRBS sequence
001: 2^9-1 bits PRBS sequence
010: 2^11-1 bits PRBS sequence
011: 2^15-1 bits PRBS sequence
100: 2^23-1 bits PRBS sequence
101: 2^31-1 bits PRBS sequence
110: 2^58-1 bits PRBS sequence
111: 2^63-1 bits PRBS sequence"
0 0 RW N PRBS_PATTERN_SEL[0]
31 7 0 RW N prbs_int_en 1: Enables interrupt for detection of PRBS errors. The PRBS checker must be properly configured for this feature to work
6 0 RW Y ADAPT_MODE1 00: no adaption
01: adapt CTLE only
10: adapt CTLE until optimal, then DFE, then CTLE again
11: adapt CTLE until lock, then DFE, then EQ until optimal
Note: for ADAPT_MODE=2 or 3, the DFE must be enabled by setting Reg_0x1E[3]=0 and Reg_0x1E[1]=1.
5 1 RW Y ADAPT_MODE0
4 0 RW Y EQ_SM_FOM1 00: not valid
01: SM uses HEO only
10: SM uses VEO only
11: SM uses both HEO and VEO
3 0 RW Y EQ_SM_FOM0
2 0 RW N RESERVED
1 0 RW Y cdr_lock_loss_int_en Enable for CDR Lock Loss Interrupt. Observable in reg_1[5]
0 0 RW Y signal_det_loss_int_en Enable for Signal Detect Loss Interrupt. Observable in reg_1[0]
32 7 0 RW Y HEO_INT_THRESH3 These bits set the threshold for the HEO and VEO interrupt. Each threshold bit represents 8 counts of HEO or VEO.
6 0 RW Y HEO_INT_THRESH2
5 0 RW Y HEO_INT_THRESH1
4 1 RW Y HEO_INT_THRESH0
3 0 RW Y VEO_INT_THRESH3
2 0 RW Y VEO_INT_THRESH2
1 0 RW Y VEO_INT_THRESH1
0 1 RW Y VEO_INT_THRESH0
33 7 1 RW Y HEO_THRESH3 In adapt mode 3, the register sets the minimum HEO and VEO required for CTLE adaption, before starting DFE adaption. This can be a max of 15.
6 0 RW Y HEO_THRESH2
5 0 RW Y HEO_THRESH1
4 0 RW Y HEO_THRESH0
3 1 RW Y VEO_THRESH3
2 0 RW Y VEO_THRESH2
1 0 RW Y VEO_THRESH1
0 0 RW Y VEO_THRESH0
34 7 0 R N PPM_ERR_RDY 1: Indicates that a PPM error count is read to be read from channel register 0x3B and 0x3C
6 0 RW Y LOW_POWER_MODE_DISABLE By default, all blocks (except signal detect) power down after 100 ms after signal detect goes low.
After achieving lock, the CDR continues to monitor the lock criteria. If the lock criteria fail, the lock is checked for a total of N number of times before declaring an out of lock condition, where N is set by this the value in these registers, with a max value of +3, for a total of 4. If during the N lock checks, lock is regained, then the lock condition is left HI, and the counter is reset back to zero.
5 1 RW Y LOCK_COUNTER1
4 1 RW Y LOCK_COUNTER0
3 1 RW Y DFE_MAX_TAP2_5[3] These four bits are used to set the maximum value by which DFE taps 2-5 are able to adapt with each subsequent adaptation. Same used for both polarities.
2 1 RW Y DFE_MAX_TAP2_5[2]
1 1 RW Y DFE_MAX_TAP2_5[1]
0 1 RW Y DFE_MAX_TAP2_5[0]
35 7 0 RW Y DATA_LOCK_PPM1 Modifies the value of the ppm delta tolerance from channel register 0x64:
00 - ppm_delta[7:0] =1 x ppm_delta[7:0]
01 - ppm_delta[7:0] =1 x ppm_delta[7:0] + ppm_delta[3:1]
10 - ppm_delta[7:0] =2 x ppm_delta[7:0]
11 - ppm_delta[7:0] =2 x ppm_delta[7:0] + ppm_delta[3:1]
6 0 RW Y DATA_LOCK_PPM0
5 0 RW N GET_PPM_ERROR Get ppm error from ppm_count - clears when done.
Normally updates continuously, but can be manually triggered with read value from channel register0x3B and 0x3C
Determines max tap limit for DFE tap 1
4 0 RW Y DFE_MAX_TAP1[4]
3 1 RW Y DFE_MAX_TAP1[3]
2 1 RW Y DFE_MAX_TAP1[2]
1 1 RW Y DFE_MAX_TAP1[1]
0 1 RW Y DFE_MAX_TAP1[0]
36 7 0 RW N RESERVED
6 0 RW Y HEO_VEO_INT_EN 1: Enable HEO/VEO interrupt capability
5 1 RW Y REF_MODE1 11: Normal Operation
4 1 RW Y REF_MODE0
3 0 RW N RESERVED
2 0 RW Y RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
37 7 0 R N CTLE_STATUS7 Feature is reserved for future use
6 0 R N CTLE_STATUS6
5 0 R N CTLE_STATUS5
4 0 R N CTLE_STATUS4
3 0 R N CTLE_STATUS3
2 0 R N CTLE_STATUS2
1 0 R N CTLE_STATUS1
0 0 R N CTLE_STATUS0
38 7 0 R N DFE_STATUS7 Feature is reserved for future use
6 0 R N DFE_STATUS6
5 0 R N DFE_STATUS5
4 0 R N DFE_STATUS4
3 0 R N DFE_STATUS3
2 0 R N DFE_STATUS2
1 0 R N DFE_STATUS1
0 0 R N DFE_STATUS0
39 7 0 RW N RESERVED RESERVED
6 1 RW Y MR_EOM_RATE1 With eom_ov = 1, these bits control the Eye Monitor Rate:
11: Use for full rate, fastest
10: Use for 1/2 Rate
All other values are reserved
5 1 RW Y MR_EOM_RATE0
4 0 RW Y RESERVED RESERVED
3 0 RW Y START_INDEX[3] Start index for EQ adaptation
2 0 RW Y START_INDEX[2]
1 0 RW Y START_INDEX[1]
0 0 RW Y START_INDEX[0]

Table 13. Channel Registers, 3A to A9

ADDRESS
(Hex)		 BITS DEFAULT
VALUE
(Hex)		 MODE EEPROM FIELD NAME DESCRIPTION
3A 7 0 RW Y FIXED_EQ_BST0[1] During adaptation, if the divider setting is >2, then a fixed EQ setting from this register will be used. However, if channel register 0x6F[7] is enabled, then an EQ adaptation will be performed instead
6 0 RW Y FIXED_EQ_BST0[0]
5 0 RW Y FIXED_EQ_BST1[1]
4 0 RW Y FIXED_EQ_BST1[0]
3 0 RW Y FIXED_EQ_BST2[1]
2 0 RW Y FIXED_EQ_BST2[0]
1 0 RW Y FIXED_EQ_BST3[1]
0 0 RW Y FIXED_EQ_BST3[0]
3B 7 0 R N ppm_count[15] PPM count MSB
6 0 R N ppm_count[14]
5 0 R N ppm_count[13]
4 0 R N ppm_count[12]
3 0 R N ppm_count[11]
2 0 R N ppm_count[10]
1 0 R N ppm_count[9]
0 0 R N ppm_count[8]
3C 7 0 R N ppm_count[7] PPM count LSB
6 0 R N ppm_count[6]
5 0 R N ppm_count[5]
4 0 R N ppm_count[4]
3 0 R N ppm_count[3]
2 0 R N ppm_count[2]
1 0 R N ppm_count[1]
0 0 R N ppm_count[0]
3D 7 0 RW Y EN_FIR_CURSOR 1: Enable Pre- and Post-cursor FIR
0: Disable Pre- and Post-cursor FIR (lower power)
6 0 RW Y FIR_C0_SGN Main-cursor sign bit
0: positive
1: negative
5 0 RW Y RESERVED RESERVED
4 1 RW Y FIR_C0[4] Main-cursor magnitude
3 1 RW Y FIR_C0[3] Main-cursor magnitude
2 0 RW Y FIR_C0[2] Main-cursor magnitude
1 1 RW Y FIR_C0[1] Main-cursor magnitude
0 0 RW Y FIR_C0[0] Main-cursor magnitude
3E 7 0 RW Y FIR_PD_TX
6 1 RW Y FIR_CN1_SGN Pre-cursor sign bit
1: negative
0: positive
5 0 RW Y RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 0 RW Y FIR_CN1[3] Pre-cursor magnitude
2 0 RW Y FIR_CN1[2] Pre-cursor magnitude
1 0 RW Y FIR_CN1[1] Pre-cursor magnitude
0 0 RW Y FIR_CN1[0] Pre-cursor magnitude
3F 7 0 RW Y RESERVED
6 1 RW Y FIR_CP1_SGN Post-cursor sign bit
1: negative
0: positive
5 0 RW Y RESERVED
4 0 RW Y RESERVED
3 0 RW Y FIR_CP1[3] Post-cursor magnitude
2 0 RW Y FIR_CP1[2] Post-cursor magnitude
1 0 RW Y FIR_CP1[1] Post-cursor magnitude
0 0 RW Y FIR_CP1[0] Post-cursor magnitude
40 7 0 RW Y EQ_ARRAY_INDEX_0_BST0[1]
6 0 RW Y EQ_ARRAY_INDEX_0_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_0_BST1[1]
4 0 RW Y EQ_ARRAY_INDEX_0_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_0_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_0_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_0_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_0_BST3[0]
41 7 0 RW Y EQ_ARRAY_INDEX_1_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_1_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_1_BST1[1]
4 0 RW Y EQ_ARRAY_INDEX_1_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_1_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_1_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_1_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_1_BST3[0]
42 7 0 RW Y EQ_ARRAY_INDEX_2_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_2_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_2_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_2_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_2_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_2_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_2_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_2_BST3[0]
43 7 1 RW Y EQ_ARRAY_INDEX_3_BST0[1]
6 0 RW Y EQ_ARRAY_INDEX_3_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_3_BST1[1]
4 0 RW Y EQ_ARRAY_INDEX_3_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_3_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_3_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_3_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_3_BST3[0]
44 7 1 RW Y EQ_ARRAY_INDEX_4_BST0[1]
6 0 RW Y EQ_ARRAY_INDEX_4_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_4_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_4_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_4_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_4_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_4_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_4_BST3[0]
45 7 1 RW Y EQ_ARRAY_INDEX_5_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_5_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_5_BST1[1]
4 0 RW Y EQ_ARRAY_INDEX_5_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_5_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_5_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_5_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_5_BST3[0]
46 7 1 RW Y EQ_ARRAY_INDEX_6_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_6_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_6_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_6_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_6_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_6_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_6_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_6_BST3[0]
47 7 1 RW Y EQ_ARRAY_INDEX_7_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_7_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_7_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_7_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_7_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_7_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_7_BST3[1]
0 1 RW Y EQ_ARRAY_INDEX_7_BST3[0]
48 7 1 RW Y EQ_ARRAY_INDEX_8_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_8_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_8_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_8_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_8_BST2[1]
2 1 RW Y EQ_ARRAY_INDEX_8_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_8_BST3[1]
0 1 RW Y EQ_ARRAY_INDEX_8_BST3[0]
49 7 1 RW Y EQ_ARRAY_INDEX_9_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_9_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_9_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_9_BST1[0]
3 1 RW Y EQ_ARRAY_INDEX_9_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_9_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_9_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_9_BST3[0]
4A 7 1 RW Y EQ_ARRAY_INDEX_10_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_10_BST0[0]
5 1 RW Y EQ_ARRAY_INDEX_10_BST1[1]
4 0 RW Y EQ_ARRAY_INDEX_10_BST1[0]
3 1 RW Y EQ_ARRAY_INDEX_10_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_10_BST2[0]
1 1 RW Y EQ_ARRAY_INDEX_10_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_10_BST3[0]
4B 7 1 RW Y EQ_ARRAY_INDEX_11_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_11_BST0[0]
5 1 RW Y EQ_ARRAY_INDEX_11_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_11_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_11_BST2[1]
2 1 RW Y EQ_ARRAY_INDEX_11_BST2[0]
1 1 RW Y EQ_ARRAY_INDEX_11_BST3[1]
0 1 RW Y EQ_ARRAY_INDEX_11_BST3[0]
4C 7 1 RW Y EQ_ARRAY_INDEX_12_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_12_BST0[0]
5 1 RW Y EQ_ARRAY_INDEX_12_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_12_BST1[0]
3 1 RW Y EQ_ARRAY_INDEX_12_BST2[1]
2 1 RW Y EQ_ARRAY_INDEX_12_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_12_BST3[1]
0 1 RW Y EQ_ARRAY_INDEX_12_BST3[0]
4D 7 1 RW Y EQ_ARRAY_INDEX_13_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_13_BST0[0]
5 1 RW Y EQ_ARRAY_INDEX_13_BST1[1]
4 0 RW Y EQ_ARRAY_INDEX_13_BST1[0]
3 1 RW Y EQ_ARRAY_INDEX_13_BST2[1]
2 1 RW Y EQ_ARRAY_INDEX_13_BST2[0]
1 1 RW Y EQ_ARRAY_INDEX_13_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_13_BST3[0]
4E 7 1 RW Y EQ_ARRAY_INDEX_14_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_14_BST0[0]
5 1 RW Y EQ_ARRAY_INDEX_14_BST1[1]
4 0 RW Y EQ_ARRAY_INDEX_14_BST1[0]
3 1 RW Y EQ_ARRAY_INDEX_14_BST2[1]
2 1 RW Y EQ_ARRAY_INDEX_14_BST2[0]
1 1 RW Y EQ_ARRAY_INDEX_14_BST3[1]
0 1 RW Y EQ_ARRAY_INDEX_14_BST3[0]
4F 7 1 RW Y EQ_ARRAY_INDEX_15_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_15_BST0[0]
5 1 RW Y EQ_ARRAY_INDEX_15_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_15_BST1[0]
3 1 RW Y EQ_ARRAY_INDEX_15_BST2[1]
2 1 RW Y EQ_ARRAY_INDEX_15_BST2[0]
1 1 RW Y EQ_ARRAY_INDEX_15_BST3[1]
0 1 RW Y EQ_ARRAY_INDEX_15_BST3[0]
50 7 1 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 1 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
51 7 1 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 0 RW N RESERVED
2 0 RW N RESERVED
1 1 RW N RESERVED
0 0 RW N RESERVED
52 7 1 RW N RESERVED
6 0 RW N RESERVED
5 1 RW N RESERVED
4 0 RW N RESERVED
3 0 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
53 7 0 RW N RESERVED
6 1 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 0 RW N RESERVED
2 1 RW N RESERVED
1 1 RW N RESERVED
0 0 RW N RESERVED
54 7 0 RW N RESERVED
6 1 RW N RESERVED
5 0 RW N RESERVED
4 1 RW N RESERVED
3 0 RW N RESERVED
2 0 RW N RESERVED
1 1 RW N RESERVED
0 0 RW N RESERVED
55 7 1 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 1 RW N RESERVED
2 1 RW N RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
56 7 1 RW N RESERVED
6 0 RW N RESERVED
5 1 RW N RESERVED
4 1 RW N RESERVED
3 0 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
57 7 1 RW N RESERVED
6 1 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 1 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
58 7 0 RW N RESERVED
6 1 RW N RESERVED
5 0 RW N RESERVED
4 1 RW N RESERVED
3 0 RW N RESERVED
2 1 RW N RESERVED
1 1 RW N RESERVED
0 1 RW N RESERVED
59 7 0 RW N RESERVED
6 1 RW N RESERVED
5 0 RW N RESERVED
4 1 RW N RESERVED
3 1 RW N RESERVED
2 1 RW N RESERVED
1 0 RW N RESERVED
0 1 RW N RESERVED
5A 7 0 RW N RESERVED
6 1 RW N RESERVED
5 1 RW N RESERVED
4 0 RW N RESERVED
3 1 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 1 RW N RESERVED
5B 7 0 RW N RESERVED
6 1 RW N RESERVED
5 1 RW N RESERVED
4 1 RW N RESERVED
3 0 RW N RESERVED
2 1 RW N RESERVED
1 0 RW N RESERVED
0 1 RW N RESERVED
5C 7 1 RW N RESERVED
6 1 RW N RESERVED
5 0 RW N RESERVED
4 1 RW N RESERVED
3 0 RW N RESERVED
2 1 RW N RESERVED
1 0 RW N RESERVED
0 1 RW N RESERVED
5D 7 1 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 1 RW N RESERVED
3 1 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 1 RW N RESERVED
5E 7 1 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 1 RW N RESERVED
3 0 RW N RESERVED
2 1 RW N RESERVED
1 1 RW N RESERVED
0 0 RW N RESERVED
5F 7 1 RW N RESERVED
6 0 RW N RESERVED
5 1 RW N RESERVED
4 0 RW N RESERVED
3 0 RW N RESERVED
2 1 RW N RESERVED
1 0 RW N RESERVED
0 1 RW N RESERVED
60 7 0 RW Y GRP0_OV_CNT7 Group 0 count LSB
6 0 RW Y GRP0_OV_CNT6
5 0 RW Y GRP0_OV_CNT5
4 0 RW Y GRP0_OV_CNT4
3 0 RW Y GRP0_OV_CNT3
2 0 RW Y GRP0_OV_CNT2
1 0 RW Y GRP0_OV_CNT1
0 0 RW Y GRP0_OV_CNT0
61 7 0 RW Y CNT_DLTA_OV_0 Override enable for group 0 manual data rate selection
6 0 RW Y GRP0_OV_CNT14 Group 0 count MSB
5 0 RW Y GRP0_OV_CNT13
4 0 RW Y GRP0_OV_CNT12
3 0 RW Y GRP0_OV_CNT11
2 0 RW Y GRP0_OV_CNT10
1 0 RW Y GRP0_OV_CNT9
0 0 RW Y GRP0_OV_CNT8
62 7 0 RW Y GRP1_OV_CNT7 Group 1 count LSB
6 0 RW Y GRP1_OV_CNT6
5 0 RW Y GRP1_OV_CNT5
4 0 RW Y GRP1_OV_CNT4
3 0 RW Y GRP1_OV_CNT3
2 0 RW Y GRP1_OV_CNT2
1 0 RW Y GRP1_OV_CNT1
0 0 RW Y GRP1_OV_CNT0
63 7 0 RW Y CNT_DLTA_OV_1 Override enable for group 1 manual data rate selection
6 0 RW Y GRP1_OV_CNT14 Group 1 count MSB
5 0 RW Y GRP1_OV_CNT13
4 0 RW Y GRP1_OV_CNT12
3 0 RW Y GRP1_OV_CNT11
2 0 RW Y GRP1_OV_CNT10
1 0 RW Y GRP1_OV_CNT9
0 0 RW Y GRP1_OV_CNT8
64 7 0 RW Y GRP0_OV_DLTA3 Sets the PPM delta tolerance for the PPM counter lock check for group 0. Must also program channel register 0x67[7].
6 0 RW Y GRP0_OV_DLTA2
5 0 RW Y GRP0_OV_DLTA1
4 0 RW Y GRP0_OV_DLTA0
3 0 RW Y GRP1_OV_DLTA3 Sets the PPM delta tolerance for the PPM counter lock check for group 1. Must also program channel register 0x67[6].
2 0 RW Y GRP1_OV_DLTA2
1 0 RW Y GRP1_OV_DLTA1
0 0 RW Y GRP1_OV_DLTA0
65 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
66 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
67 7 0 RW Y GRP0_OV_DLTA[4]
6 0 RW Y GRP1_OV_DLTA[4]
5 1 RW Y HV_LOCKMON_EN 1: Enable periodic monitoring of HEO/VEO for lock qualification.
0: Disable periodic HEO/VEO monitoring for lock qualification.
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
68 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
69 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 1 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
6A 7 0 RW Y VEO_LCK_THRSH3 VEO threshold to meet before lock is established. The LSB step size is 4 counts of VEO.
6 0 RW Y VEO_LCK_THRSH2
5 1 RW Y VEO_LCK_THRSH1
4 0 RW Y VEO_LCK_THRSH0
3 0 RW Y HEO_LCK_THRSH3 HEO threshold to meet before lock is established. The LSB step size is 4 counts of VEO.
2 0 RW Y HEO_LCK_THRSH2
1 1 RW Y HEO_LCK_THRSH1
0 0 RW Y HEO_LCK_THRSH0
6B 7 0 RW Y RESERVED RESERVED
6 1 RW Y FOM_A6 Alternate Figure of Merit variable A. Max value for this register is 128.
5 0 RW Y FOM_A5
4 0 RW Y FOM_A4
3 0 RW Y FOM_A3
2 0 RW Y FOM_A2
1 0 RW Y FOM_A1
0 0 RW Y FOM_A0
6C 7 0 RW Y FOM_B7 HEO adjustment for Alternate FoM, variable B
6 0 RW Y FOM_B6
5 0 RW Y FOM_B5
4 0 RW Y FOM_B4
3 0 RW Y FOM_B3
2 0 RW Y FOM_B2
1 0 RW Y FOM_B1
0 0 RW Y FOM_B0
6D 7 0 RW Y FOM_C7 VEO adjustment for Alternate FoM, variable C
6 0 RW Y FOM_C6
5 0 RW Y FOM_C5
4 0 RW Y FOM_C4
3 0 RW Y FOM_C3
2 0 RW Y FOM_C2
1 0 RW Y FOM_C1
0 0 RW Y FOM_C0
6E 7 0 RW Y EN_NEW_FOM_CTLE 1: CTLE adaption state machine will use the alternate FoM
HEO_ALT = (HEO-B)*A*2VEO_ALT = (VEO-C)*(1-A)*2
The values of A,B,C are set in channel register 0x6B, 0x6C, and 0x6D.
The value of A is equal to the register value divided by 128.
The Alternate FoM = (HEOB)*A*2 + (VEO-C)*(1-A)*2
6 0 RW Y EN_NEW_FOM_DFE 1: DFE adaption state machine will use the alternate FoM.
HEO_ALT = (HEO-B)*A*2VEO_ALT = (VEO-C)*(1-A)*2
The values of A,B,C are set in channel register 0x6B, 0x6C, and 0x6D.
The value of A is equal to the register value divided by 128
The Alternate FoM = (HEOB)*A*2 + (VEO-C)*(1-A)*2
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
6F 7 0 RW Y MR_EN_LOW_DIVSEL_EQ Normally, during adaptation, if the divider setting is >2, then a fixed EQ setting, from Reg_0x3A will be used. However, if Reg_0x6F[7]=1, then an EQ adaptation will be performed instead.
6 0 RW Y RESERVED RESERVED
5 0 RW Y RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
70 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW Y EQ_LB_CNT[3] CTLE look-beyond count for adaptation
2 1 RW Y EQ_LB_CNT[2]
1 0 RW Y EQ_LB_CNT[1]
0 1 RW Y EQ_LB_CNT[0]
71 7 0 R N PRBS_INT When enabled by Reg_0x31[7], goes HI if a PRBS stream is detected. Clears on reading.
PRBS checker must be enabled with Reg_0x30[3].
Once cleared, if a PRBS error occurs, then the interrupt will again go HI. Clears on reading.
If signal detect is lost, this is considered a PRBS error, and the interrupt will go HI. Clears on reading.
6 0 R N RESERVED RESERVED
5 0 R N DFE_POL_1_OBS DFE tap 1 polarity observation
4 0 R N DFE_WT1_OBS[4] DFE tap 1 weight observation
3 0 R N DFE_WT1_OBS[3]
2 0 R N DFE_WT1_OBS[2]
1 0 R N DFE_WT1_OBS[1]
0 0 R N DFE_WT1_OBS[0]
72 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N DFE_POL_2_OBS Primary observation point for DFE tap 2 polarity
3 0 R N DFE_WT2_OBS3 Primary observation point for DFE tap 2 weight
2 0 R N DFE_WT2_OBS2
1 0 R N DFE_WT2_OBS1
0 0 R N DFE_WT2_OBS0
73 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N DFE_POL_3_OBS Primary observation point for DFE tap 3 polarity
3 0 R N DFE_WT3_OBS3 Primary observation point for DFE tap 3 weight
2 0 R N DFE_WT3_OBS2
1 0 R N DFE_WT3_OBS1
0 0 R N DFE_WT3_OBS0
74 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N DFE_POL_4_OBS Primary observation point for DFE tap 4 polarity
3 0 R N DFE_WT4_OBS3 Primary observation point for DFE tap 4 weight
2 0 R N DFE_WT4_OBS2
1 0 R N DFE_WT4_OBS1
0 0 R N DFE_WT4_OBS0
75 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N DFE_POL_5_OBS Primary observation point for DFE tap 5 polarity
3 0 R N DFE_WT5_OBS3 Primary observation point for DFE tap 5 weight
2 0 R N DFE_WT5_OBS2
1 0 R N DFE_WT5_OBS1
0 0 R N DFE_WT5_OBS0
76 7 0 RW Y post_lock_veo_thr[3] VEO threshold after LOCK is established
6 0 RW Y post_lock_veo_thr[2]
5 1 RW Y post_lock_veo_thr[1]
4 0 RW Y post_lock_veo_thr[0]
3 0 RW Y post_lock_heo_thr[3] HEO threshold after LOCK is established
2 0 RW Y post_lock_heo_thr[2]
1 0 RW Y post_lock_heo_thr[1]
0 1 RW Y post_lock_heo_thr[0]
77 7 0 RW N PRBS_GEN_POL_EN 1: Force polarity inversion on generated PRBS data
6 0 RW Y RESERVED
5 0 RW Y RESERVED
4 1 RW Y RESERVED
3 1 RW Y RESERVED
2 0 RW Y RESERVED
1 1 RW Y RESERVED
0 0 RW N RESERVED
78 7 0 R N RESERVED
6 0 R N RESERVED
5 0 R N SD_STATUS Primary observation point forsignal detect status
4 0 R N CDR_LOCK_STATUS Primary observation point forCDR lock status
3 0 R N CDR_LOCK_INT Requires that channel register 0x79[1] be set.
1: Indicates CDR has achieved lock, lock goes from LOW to HIGH. This bit is cleared after reading. This bit will stay set until it has been cleared by reading.
2 0 R N SD_INT Requires that channel register 0x79[0] be set.
1: Indicates signal detect status has changed. This will trigger when signal detect goes from LOW to HIGH or HIGH to LOW. This bit is cleared after reading. This bit will stay set until it has been cleared by reading.
1 0 R N EOM_VRANGE_LIMIT_ERROR Goes high if GET_HEO_VEO indicates high during adaptation
0 0 R N HEO_VEO_INT Requires that channel register 0x36[6] be set.
1: Indicates that HEO/VEO dropped below the limits set in channel register 0x76 This bit is cleared after reading. This bit will stay set until it has been cleared by reading.
79 7 0 RW N RESERVED
6 0 RW N PRBS_CHKR_EN 1: Enable the PRBS checker.
0: Disable the PRBS checker
5 0 RW N PRBS_GEN_EN 1: Enable the pattern generator
0: Disable the pattern generator
4 1 RW N PRBS_LCKUP_EXIT_EN 0: Turn off lock up detection in PRBS checker/generator
Used for debug purposes only.
3 0 RW N RESERVED
2 0 RW N RESERVED
1 0 RW Y CDR_LOCK_INT_EN 1: Enable CDR lock interrupt, observable in channel register 0x78[3]
0: Disable CDR lock interrupt
0 0 RW Y SD_INT_EN 1: Enable signal detect interrupt, observable in channel register 0x78[3]
0: Disable signal detect interrupt
7A 7 0 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 0 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
7B 7 0 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 0 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
7C 7 0 R N PRBS_FIXED7 Pattern generator user defined pattern LSB. MSB located at channel register 0x97.
6 0 R N PRBS_FIXED6
5 0 R N PRBS_FIXED5
4 0 R N PRBS_FIXED4
3 0 R N PRBS_FIXED3
2 0 R N PRBS_FIXED2
1 0 R N PRBS_FIXED1
0 0 R N PRBS_FIXED0
7D 7 0 RW Y CONT_ADAPT_HEO_CHNG_THRS3 Limit for HEO change before triggering a DFE adaption while continuous DFE adaption is enabled.
6 1 RW Y CONT_ADAPT_HEO_CHNG_THRS2
5 0 RW Y CONT_ADAPT_HEO_CHNG_THRS1
4 0 RW Y CONT_ADAPT_HEO_CHNG_THRS0
3 1 RW Y CONT_ADAPT_VEO_CHNG_THRS3 Limit for VEO change before triggering a DFE adaption while continuous DFE adaption is enabled
2 0 RW Y CONT_ADAPT_VEO_CHNG_THRS2
1 0 RW Y CONT_ADAPT_VEO_CHNG_THRS1
0 0 RW Y CONT_ADAPT_VEO_CHNG_THRS0
7E 7 0 RW Y CONT_ADPT_TAP_INCR3 Limit for allowable tap increase from the previous base point
6 0 RW Y CONT_ADPT_TAP_INCR2
5 0 RW Y CONT_ADPT_TAP_INCR1
4 1 RW Y CONT_ADPT_TAP_INCR0
3 0 RW Y CONT_ADPT_FOM_CHNG_THRS3 Bits define by how much the FOM can change before triggering DFE adapt
2 0 RW Y CONT_ADPT_FOM_CHNG_THRS2
1 1 RW Y CONT_ADPT_FOM_CHNG_THRS1
0 1 RW Y CONT_ADPT_FOM_CHNG_THRS0
7F 7 0 RW N EN_OBS_ALT_FOM 1: Allows for alternate FoM 7Fcalculation to be shown in channel registers 0x27, 0x28 and 0x29 instead of HEO and VEO
6 0 RW N RESERVED
5 1 RW Y DIS_HV_CHK_FOR_CONT_ADAPT 1: Ignore HEO/VEO lock condition checks during continuous adaption. Normal operation for continuous DFE adaption
4 0 RW Y EN_DFE_CONT_ADAPT 1: Continuous DFE adaption is enabled
0: DFE adapts only during lock and then freezes
3 1 RW Y CONT_ADPT_CMP_BOTH 1: If continuous DFE adaption is enabled, a DFE adaption will trigger if either HEO orVEO degrades
2 0 RW Y CONT_ADPT_COUNT2 Limit for number of weights the DFE can look ahead in continuous adaption
1 1 RW Y CONT_ADPT_COUNT1
0 0 RW Y CONT_ADPT_COUNT0
80 7 0 R N RESERVED
6 0 R N RESERVED
5 0 R N RESERVED
4 0 R N RESERVED
3 0 R N RESERVED
2 0 R N RESERVED
1 0 R N RESERVED
0 0 R N RESERVED
81 7 1 R N RESERVED RESERVED
6 1 R N RESERVED RESERVED
5 1 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 1 R N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 0 R N RESERVED RESERVED
82 7 0 RW N FREEZE_PRBS_CNTR 1: Freeze the PRBS error count to allow for readback.
0: Normal operation. Error counters is allowed to increment if the PRBS checker is properly configured
6 0 RW N RST_PRBS_CNTS 1: Reset the PRBS error counter.
0: Normal operation. Error counter is released from reset.
5 0 RW N PRBS_PATT_OV 1: Override PRBS pattern auto-detection. Forces the pattern checker to only lock onto the pattern defined in Reg_0x82[4:2].
0: Normal operation. Pattern checker will automatically detect the PRBS pattern
4 0 RW N PRBS_PATT[2] Used with the PRBS checker. Usage is enabled with Reg_0x82[5]. Select PRBS pattern to be checked:
000 - PRBS7
001 - PRBS9
010 - PRBS11
011 - PRBS15
100 - PRBS23
101 - PRBS31
110 - PRBS58
111 - PRBS63
3 0 RW N PRBS_PATT[1]
2 0 RW N PRBS_PATT[0]
1 0 RW N PRBS_POL_OV 1: Override PRBS pattern auto polarity detection. Forces the pattern checker to only lock onto the polarity defined in bit 0 of this register.
0: Normal operation, pattern checker will automatically detect the PRBS pattern polarity
0 0 RW N PRBS_POL Usage is enabled with Reg_0x82[1]=1
0: Forced polarity = true
1: Forced polarity = inverted
83 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 0 R N PRBS_ERR_CNT[10] PRBS checker error count
1 0 R N PRBS_ERR_CNT[9] PRBS checker error count
0 0 R N PRBS_ERR_CNT[8] PRBS checker error count
84 7 0 R N PRBS_ERR_CNT7 PRBS checker error count
6 0 R N PRBS_ERR_CNT6
5 0 R N PRBS_ERR_CNT5
4 0 R N PRBS_ERR_CNT4
3 0 R N PRBS_ERR_CNT3
2 0 R N PRBS_ERR_CNT2
1 0 R N PRBS_ERR_CNT1
0 0 R N PRBS_ERR_CNT0
85 7 0 R N RESERVED
6 0 R N RESERVED
5 0 R N RESERVED
4 0 R N RESERVED
3 0 R N RESERVED
2 0 R N RESERVED
1 0 R N RESERVED
0 0 R N RESERVED
86 7 0 R N RESERVED
6 0 R N RESERVED
5 0 R N RESERVED
4 0 R N RESERVED
3 0 R N RESERVED
2 0 R N RESERVED
1 0 R N RESERVED
0 0 R N RESERVED
87 7 0 R N RESERVED
6 0 R N RESERVED
5 0 R N RESERVED
4 0 R N RESERVED
3 0 R N RESERVED
2 0 R N RESERVED
1 0 R N RESERVED
0 0 R N RESERVED
88 7 0 R N RESERVED
6 0 R N RESERVED
5 0 R N RESERVED
4 0 R N RESERVED
3 0 R N RESERVED
2 0 R N RESERVED
1 0 R N RESERVED
0 0 R N RESERVED
89 7 0 R N RESERVED
6 0 R N RESERVED
5 0 R N RESERVED
4 0 R N RESERVED
3 0 R N RESERVED
2 0 R N RESERVED
1 0 R N RESERVED
0 0 R N RESERVED
8A 7 0 R N RESERVED
6 0 R N RESERVED
5 0 R N RESERVED
4 0 R N RESERVED
3 0 R N RESERVED
2 0 R N RESERVED
1 0 R N RESERVED
0 0 R N RESERVED
8B 7 0 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 0 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
8C 7 0 RW N UNCORR_ERR_PATT7 Used in conjunction with register 0x78[7]. This register, register 0x8B and register 0x8C set a 16-bit pattern that is searched for within the data stream. If this pattern is found, the interrupt in register 0x78[7] is set HI.
6 0 RW N UNCORR_ERR_PATT6
5 0 RW N UNCORR_ERR_PATT5
4 0 RW N UNCORR_ERR_PATT4
3 0 RW N UNCORR_ERR_PATT3
2 0 RW N UNCORR_ERR_PATT2
1 0 RW N UNCORR_ERR_PATT1
0 0 RW N UNCORR_ERR_PATT0
8D 7 0 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 0 RW N RESERVED
2 1 RW N RESERVED
1 1 RW N RESERVED
0 0 RW N RESERVED
8E 7 0 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 0 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 0 RW Y VGA_SEL_GAIN[0] VGA selection bit (1: on, 0: off)
8F 7 0 R N EQ_BST_TO_ANA7 Primary observation point for the EQ boost setting.
6 0 R N EQ_BST_TO_ANA6
5 0 R N EQ_BST_TO_ANA5
4 0 R N EQ_BST_TO_ANA4
3 0 R N EQ_BST_TO_ANA3
2 0 R N EQ_BST_TO_ANA2
1 0 R N EQ_BST_TO_ANA1
0 0 R N EQ_BST_TO_ANA0
90 7 0 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 0 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
91 7 0 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 0 RW N RESERVED
2 0 RW N RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
92 7:0 0 RW N RESERVED
93 7:0 0 RW N RESERVED
94 7:0 0 RW N RESERVED
95 7:0 0 RW N RESERVED
96 7 0 RW N RESERVED
6 0 RW N RESERVED
5 0 RW N RESERVED
4 0 RW N RESERVED
3 1 RW Y EQ_EN_LOCAL 1: Enable the ebuf for the local output. Can be set independently of other controls.
2 0 RW Y EQ_EN_FANOUT 1: Enable the ebuf for the fanout. Can be set independently of other controls.
1 0 RW Y EQ_SEL_XPNT 1: Indicates to a channel where it is getting its data from. 0 indicates local. 1-indicates from the cross.
0 0 RW Y XPNT_SLAVE 1: Indicates to a channel if it needs to wait for the other channel to complete its lock/adaptation. The need for this condition comes up when input of one channel is routed to the other channel or multiple channels.
97 7 0 R N PRBS_FIXED15 Pattern generator user defined pattern MSB. LSB located at channel register 0x7C.
6 0 R N PRBS_FIXED14
5 0 R N PRBS_FIXED13
4 0 R N PRBS_FIXED12
3 0 R N PRBS_FIXED11
2 0 R N PRBS_FIXED10
1 0 R N PRBS_FIXED9
0 0 R N PRBS_FIXED8
98 7:6 0 RW N RESERVED
5:0 0 RW Y RESERVED
99 7 0 RW Y RESERVED
6 0 RW Y RESERVED
5 1 RW Y RESERVED
4 1 RW Y RESERVED
3 1 RW Y RESERVED
2 1 RW Y RESERVED
1 1 RW Y RESERVED
0 1 RW Y RESERVED
9A 7 0 RW Y RESERVED
6 0 RW Y RESERVED
5 1 RW Y RESERVED
4 1 RW Y RESERVED
3 1 RW Y RESERVED
2 1 RW Y RESERVED
1 1 RW Y RESERVED
0 1 RW Y RESERVED
9B 7 1 RW Y RESERVED
6 1 RW Y RESERVED
5 1 RW Y RESERVED
4 0 RW Y RESERVED
3 0 RW Y RESERVED
2 0 RW Y RESERVED
1 0 RW N RESERVED
0 0 RW N RESERVED
9C 7 0 RW N RESERVED
6 0 RW N RESERVED
5 1 RW Y RESERVED
4 0 RW Y RESERVED
3 0 RW Y RESERVED
2 1 RW Y RESERVED
1 0 RW Y RESERVED
0 0 RW Y RESERVED
9D 7 1 RW N RESERVED
6 0 RW N RESERVED
5 1 RW N RESERVED
4 0 RW N RESERVED
3 0 RW Y RESERVED
2 1 RW Y RESERVED
1 0 RW Y RESERVED
0 1 RW N RESERVED
9E 7 0 RW Y cp_en_idac_pd[2] Phase detector charge pump setting, when override is enabled. See reg_0C for other bits.
6 1 RW Y cp_en_idac_pd[1]
5 0 RW Y cp_en_idac_pd[0]
4 0 RW Y cp_en_idac_fd[2] Frequency detector charge pump setting, when override is enabled. See reg_0C for other bits.
3 1 RW Y cp_en_idac_fd[1]
2 0 RW Y cp_en_idac_fd[0]
1 0 RW N RESERVED
0 0 RW N RESERVED
9F 7:0 0 R N NOT USED
A0 7:0 0 R N NOT USED
A1 7:0 0 R N NOT USED
A2 7:0 0 R N NOT USED
A3 7:0 0 R N NOT USED
A4 7:0 0 R N NOT USED
A5 7 0 RW Y PFD_SEL_DATA_PSTLCK[2] Post-lock PFD mux select
111 - Mute
110 - N/A
101 - 10M Clock
100 - PRBS Generator or Fixed Pattern Generator Data
011 - N/A
010 - N/A
000 - Raw Data
6 0 RW Y PFD_SEL_DATA_PSTLCK[1]
5 1 RW Y PFD_SEL_DATA_PSTLCK[0]
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
A6 7 0 RW N INCR_HIST_TMR Provides an option to increase EOM timer given by 0x2A[7:4] for histogram collection by +8 for selection values < 8
6 1 RW Y EOM_TMR_ABRT_ON_HIT Enables faster scan through the eye-matrix by moving on to the next matrix point as soon as hit is observed
Note: This bit does not affect when slope measurement are in progress
5 0 RW Y SLP_MIN_REQ_HITS[1] Minimum required hit count for registering a hit during slope measurements.
4 0 RW Y SLP_MIN_REQ_HITS[0]
3 0 RW Y LFT_SLP 0: allows slope measurement for the right side of the eye
1: allows slope measurement for the left side of the eye
2 0 RW Y TOP_SLP 0: allows slope measurement for the bottom side of the eye
1: allows slope measurement for the top side of the eye
1 1 RW Y DFE_BATHTUB_FOM Enables slope-based bathtub FoM for DFE adaptation
0 1 RW Y CTLE_BATHTUB_FOM Enables slope-based bathtub FoM for CTLE adaptation
A7 7:0 0 R N RESERVED
A8 7:0 0 RW N RESERVED
A9 7:0 0 RW Y RESERVED