SNLS513C December   2015  – October 2019 DS250DF810

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, Retimer Jitter Specifications
    7. 7.7  Timing Requirements, Retimer Specifications
    8. 7.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 7.9  Recommended SMBus Switching Characteristics (Slave Mode)
    10. 7.10 Recommended SMBus Switching Characteristics (Master Mode)
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  AC-Coupled Receiver and Transmitter
      3. 8.3.3  Signal Detect
      4. 8.3.4  Continuous Time Linear Equalizer (CTLE)
      5. 8.3.5  Variable Gain Amplifier (VGA)
      6. 8.3.6  Cross-Point Switch
      7. 8.3.7  Decision Feedback Equalizer (DFE)
      8. 8.3.8  Clock and Data Recovery (CDR)
      9. 8.3.9  Calibration Clock
      10. 8.3.10 Differential Driver with FIR Filter
      11. 8.3.11 Setting the Output VOD
      12. 8.3.12 Output Driver Polarity Inversion
      13. 8.3.13 Debug Features
        1. 8.3.13.1 Pattern Generator
        2. 8.3.13.2 Pattern Checker
        3. 8.3.13.3 Eye Opening Monitor
      14. 8.3.14 Interrupt Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Backplane and Mid-Plane Applications
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Thermal Information

THERMAL METRIC(2) CONDITIONS/ ASSUMPTIONS(1) UNIT
4-layer JEDEC Board 10-layer 8in x 6in Board 20-layer 8in x 6in Board 30-layer 8in x 6in Board
RθJA Junction-to-ambient thermal resistance 26.4 9.3 8.5 8.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 1.6 - - -
RθJB Junction-to-board thermal resistance 9.3 - - -
ΨJT Junction-to-top characterization parameter 0.1 0.1 0.1 0.1
ΨJB Junction-to-board characterization parameter 9.3 5 4.9 4.6
(1) No heat sink or airflow was assumed for these estimations. Depending on the application, a heat sink, faster airflow, and/or reduced ambient temperature (<85 C) may be required in order to meet the maximum junction temperature specification per the Recommended Operating Conditions section.
(2) For more information about traditional and new thermal metrics, see the IC Package-Thermal Metrics application report, SPRA953.