SNLS243H September   2006  – March 2016 DS25MB100

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CML Inputs and EQ
      2. 8.3.2 Multiplexer and Loopback Control
      3. 8.3.3 CML Drivers and Pre-Emphasis Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • NJK|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The DS25MB100 is a signal-conditioning 2:1 multiplexer and a 1:2 buffer designed to support port redundancy with encoded or scrambled data rates up to 2.5 Gbps. The DS25MB100 is not designed to operate with data rates below 250 Mbps or with a DC bias applied to the CML inputs or outputs.

8.2 Functional Block Diagram

DS25MB100 20208902.gif Figure 7. Simplified Block Diagram

8.3 Feature Description

The DS25MB100 MUX buffer consists of several key blocks:

  • CML Inputs and EQ
  • Multiplexer and Loopback Control
  • CML Drivers and Pre-Emphasis Control

8.3.1 CML Inputs and EQ

The high speed inputs are self-biased to about 1.3 V at IN+ and IN– and are designed for AC coupling, allowing the DS25MB100 to be inserted directly into the datapath without any limitation. See Figure 8 for details about the internal receiver input termination and bias circuit.

DS25MB100 20209050.gif Figure 8. Receiver Input Termination and Bias Circuit

The inputs are compatible to most AC-coupling differential signals such as LVDS, LVPECL, and CML. The ideal AC-coupling capacitor value is often based on the lowest frequency component embedded within the serial link. A typical AC-coupling capacitor value ranges from 100 to 1000 nF. Some specifications with scrambled data may require a larger coupling capacitor for optimal performance. To reduce unwanted parasitics around and within the AC-coupling capacitor, TI recommends a body size of 0402. Figure 6 shows the AC-coupling capacitor placement in an AC test circuit.

Each input stage has a fixed equalizer that provides equalization to compensate about 5 dB (at 1.25 GHz) of transmission loss from a short backplane trace (about 10 inches backplane). EQ can be enabled or disabled with the EQL and EQS pins.

Table 1. EQ Controls for Line and Switch Inputs

PIN PIN VALUE EQUALIZER FUNCTION
EQL, EQS 0 Enable equalization.
1 (default) Normal mode. Equalization disabled.

8.3.2 Multiplexer and Loopback Control

Table 2 and Table 3 provide details about how to configure the DS25MB100 multiplexer and loopback settings.

Table 2. Logic Table for Multiplex Controls

PIN PIN VALUE MUX FUNCTION
MUX 0 MUX select switch input IN1±.
1 (default) MUX select switch input IN0±.

Table 3. Logic Table for Loopback Controls

PIN PIN VALUE LOOPBACK FUNCTION
LB0 0 Enable loopback from IN0± to OUT0±.
1 (default) Normal mode. Loopback disabled.
LB1 0 Enable loopback from IN1± to OUT1±.
1 (default) Normal mode. Loopback disabled.

8.3.3 CML Drivers and Pre-Emphasis Control

The output driver has pre-emphasis (driver-side equalization) to compensate the transmission loss of the backplane that it is driving. The driver conditions the output signal such that the lower frequency and higher frequency pulses reach approximately the same amplitude at the end of the backplane and minimize the deterministic jitter caused by the amplitude disparity. The DS25MB100 provides four steps of user-selectable pre-emphasis ranging from 0, –3, –6 and –9 dB to handle different lengths of backplane. Figure 9 shows a driver pre-emphasis waveform. The pre-emphasis duration is 188 ps nominal, corresponding to 0.47 unit intervals (UI) at 2.5 Gbps. The pre-emphasis levels of switch-side and line-side can be individually programmed.

DS25MB100 20209004.gif Figure 9. Driver Pre-Emphasis Differential Waveform (Showing All 4 Pre-Emphasis Steps)

Table 4. Line-Side Pre-Emphasis Controls

DEL_[1:0] PRE-EMPHASIS LEVEL IN mVPP
(VODB)		 PRE-EMPHASIS LEVEL IN mVPP
(VODPE)		 PRE-EMPHASIS IN dB
(VODPE/VODB)		 TYPICAL FR4
BOARD TRACE
0 0 1300 1300 0 10 inches
0 1 1300 920 −3 20 inches
1 0 1300 650 −6 30 inches
1 1
(default)		 1300 461 −9 40 inches

Table 5. Switch-Side Pre-Emphasis Controls

DES_[1:0] PRE-EMPHASIS LEVEL IN mVPP
(VODB)		 PRE-EMPHASIS LEVEL IN mVPP
(VODPE)		 PRE-EMPHASIS IN dB
(VODPE/VODB)		 TYPICAL FR4
BOARD TRACE
0 0 1300 1300 0 10 inches
0 1 1300 920 −3 20 inches
1 0 1300 650 −6 30 inches
1 1
(default)		 1300 461 −9 40 inches