SNLS375C June   1998  – January 2015 DS26C31T

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Device Logic Diagram
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 DC Electrical Characteristics
    4. 7.4 Switching Characteristics
    5. 7.5 Comparison Table of Switching Characteristics into “LS-Type” Load
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The DS26C31 is a quad differential line driver designed for data transmission over balanced cable or printed circuit board traces. The DS26C31M supports a temperature range of -55°C to 125°C, while the DS26C31T supports a temperature range of -40°C to 85°C.

9.2 Functional Block Diagram

DS26C31_functional_block_diagram.gif

9.3 Feature Description

Each driver converts the TTL or CMOS signal at its input to a pair of complementary differential outputs. The drivers are enabled when the ENABLE control pin is a logic HIGH or when the ENABLE control pin is a logic LOW.

9.4 Device Functional Modes

Table 1. Function Table(1)

ENABLE ENABLE INPUT NON-INVERTING OUTPUT INVERTING OUTPUT
L H X Z Z
All other combinations of enable inputs L L H
H H L
(1) L = Low logic state
X = Irrelevant
H = High logic state
Z = Tri-state (high impedance)