SNLS544B September   2016  – October 2019 DS280BR820

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics – Serial Management Bus Interface
    7. 6.7 Timing Requirements – Serial Management Bus Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 AC-Coupled Receiver Inputs
      3. 7.3.3 Signal Detect
      4. 7.3.4 2-Stage CTLE
      5. 7.3.5 Driver DC Gain Control
      6. 7.3.6 FIR Filter (Limiting Mode)
      7. 7.3.7 Configurable SMBus Address
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Slave Mode Configuration
      2. 7.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 7.5 Programming
      1. 7.5.1 Transfer of Data with the SMBus Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Types: Global, Shared, and Channel
      2. 7.6.2 Global Registers: Channel Selection and ID Information
        1. Table 2. Global Register Map
      3. 7.6.3 Shared Registers
        1. Table 3. Shared Register Map
      4. 7.6.4 Channel Registers
        1. Table 4. Channel Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Backplane and Mid-Plane Reach Extension
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Front-Port Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Pattern Generator Characteristics
        2. 8.2.3.2 Equalizing Moderate Pre-Channel Loss
        3. 8.2.3.3 Equalizing High Pre-Channel Loss
        4. 8.2.3.4 Equalizing High Pre-Channel Loss and Moderate Post-Channel Loss
        5. 8.2.3.5 Output in FIR Limiting Mode with 16T Pattern
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Stripline Example
      2. 10.2.2 Microstrip Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Signal Detect

Each DS280BR820 high speed receiver has a signal detect circuit which monitors the energy level on the inputs. The signal detect circuit will enable the high-speed data path if a signal is detected, or power it off if no signal is detected. By default, this feature is enabled, but can be manually controlled though the SMBus channel registers. This can be useful if it is desired to manually force channels to be disabled. For information on how to manually operate the signal detect circuit refer to the DS280BR820 Programming Guide.