SNLS538B September   2016  – February 2024 DS280DF810

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements, Retimer Jitter Specifications
    7. 5.7  Timing Requirements, Retimer Specifications
    8. 5.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 5.9  Recommended SMBus Switching Characteristics (Target Mode)
    10. 5.10 Recommended SMBus Switching Characteristics (Controller Mode)
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Data Path Operation
        1. 6.3.1.1 AC-Coupled Receiver and Transmitter
        2. 6.3.1.2 Signal Detect
        3. 6.3.1.3 Continuous Time Linear Equalizer (CTLE)
        4. 6.3.1.4 Variable Gain Amplifier (VGA)
        5. 6.3.1.5 2x2 Cross-Point Switch
        6. 6.3.1.6 Decision Feedback Equalizer (DFE)
        7. 6.3.1.7 Clock and Data Recovery (CDR)
        8. 6.3.1.8 Calibration Clock
        9. 6.3.1.9 Differential Driver with FIR Filter
          1. 6.3.1.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
          2. 6.3.1.9.2 Output Driver Polarity Inversion
      2. 6.3.2 Debug Features
        1. 6.3.2.1 Pattern Generator
        2. 6.3.2.2 Pattern Checker
        3. 6.3.2.3 Eye Opening Monitor
        4. 6.3.2.4 Interrupt Signals
    4. 6.4 Device Functional Modes
      1. 6.4.1 Supported Data Rates
      2. 6.4.2 SMBus Controller Mode
      3. 6.4.3 42
      4. 6.4.4 Device SMBus Address
    5. 6.5 Programming
      1. 6.5.1 Bit Fields in the Register Set
      2. 6.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 6.6 Register Maps
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Backplane and Mid-Plane Reach Extension Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Front-Port Jitter Cleaning Application
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABW|135
  • ABV|135
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-6E006817-C5DE-486F-A812-417CB84AE063-low.gif Figure 4-1 135-Pin fcBGA, 0.8mm BGA Pin Pitch (Top View)
Table 4-1 Pin Functions
PIN TYPE INTERNAL
PULL-UP/
PULL-DOWN		 DESCRIPTION
NAME NO.
HIGH SPEED DIFFERENTIAL I/Os
RX0P C15 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX0N B15 Input None
RX1P B13 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX1N A13 Input None
RX2P B11 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX2N A11 Input None
RX3P B9 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX3N A9 Input None
RX4P B7 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX4N A7 Input None
RX5P B5 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX5N A5 Input None
RX6P B3 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX6N A3 Input None
RX7P C1 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX7N B1 Input None
TX0P G15 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX0N H15 Output None
TX1P H13 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX1N J13 Output None
TX2P H11 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX2N J11 Output None
TX3P H9 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX3N J9 Output None
TX4P H7 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX4N J7 Output None
TX5P H5 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX5N J5 Output None
TX6P H3 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX6N J3 Output None
TX7P G1 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX7N H1 Output None
CALIBRATION CLOCK PINS
CAL_CLK_IN E1 Input, 2.5V CMOS Weak pull-down 25MHz (±100 PPM) 2.5V single-ended clock from external oscillator. No stringent phase noise or jitter requirements on this clock. Used to calibrate VCO frequency range. This clock is not used to recover data.
CAL_CLK_OUT E15 Output, 2.5V CMOS None 2.5V buffered replica of calibration clock input (pin E1) for connecting multiple devices in a daisy-chained fashion.
SYSTEM MANAGEMENT BUS (SMBUS) PINS
ADDR0 D13 Input, 4-level None 4-level strap pins used to set the SMBus address of the device. The pin state is read on power-up. The multi-level nature of these pins allows for 16 unique device addresses. The four strap options include:
0: 1kΩ to GND
R: 10kΩ to GND
F: Float
1: 1kΩ to VDD
Refer to Section 6.4.4 for more information.
ADDR1 E13 Input, 4-level None
EN_SMB E3 Input, 4-level None Four-level 2.5V input used to select between SMBus controller mode (float) and SMBus target mode (high). The four defined levels are:
0: 1kΩ to GND - RESERVED, TI test mode .
R: 10kΩ to GND - RESERVED, TI test mode
F: Float - SMBus Controller Mode
1: 1kΩ to VDD - SMBus Target Mode
SDA E12 I/O, 3.3V LVCMOS, Open Drain None SMBus data input and open drain output. External 2kΩ to 5kΩ pull-up resistor is required as per SMBus interface standard. This pin is 3.3V LVCMOS tolerant.
SDC F12 I/O, 3.3V LVCMOS, Open Drain None SMBus clock input and open drain clock output. External 2kΩ to 5kΩ pull-up resistor is required as per SMBus interface standard. This pin is 3.3V LVCMOS tolerant.
SMBUS MASTER MODE PINS
READ_EN_N F13 Input, 3.3V LVCMOS Weak pull-up SMBus Controller Mode (EN_SMB=Float): When asserted low, initiates the SMBus controller mode EEPROM read function. Once EEPROM read is complete (indicated by assertion of ALL_DONE_N low), this pin can be held low for normal device operation. This pin is 3.3V tolerant.
SMBus Target Mode (EN_SMB=1): When asserted low, this causes the device to be held in reset (I2C state machine reset and register reset). This pin should be pulled high or left floating for normal operation in SMBus Target Mode. This pin is 3.3V tolerant.
ALL_DONE_N D3 Output, LVCMOS None Indicates the completion of a valid EEPROM register load operation when in SMBus Controller Mode (EN_SMB=Float):
High = External EEPROM load failed or incomplete
Low = External EEPROM load successful and complete
When in SMBus target mode (EN_SMB=1), this output reflects the status of READ_EN_N input.
MISCELLANEOUS PINS
INT_N F3 Output, LVCMOS, Open-Drain None Open-drain 3.3V tolerant active-low interrupt output. It pulls low when an interrupt occurs. The events which trigger an interrupt are programmable through SMBus registers. This pin can be connected in a wired-OR fashion with other device's interrupt pin. A single pull-up resistor in the 2kΩ to 5kΩ range is adequate for the entire INT_N net.
TEST0 E2 Input, LVCMOS Weak pull-up Reserved TI test pins. During normal (non-test-mode) operation, these pins are configured as inputs and therefore they are not affected by the presence of a signal. These pins may be left floating, tied to GND, or connected to a 2.5V (max) output.
TEST1 E14 Input, LVCMOS Weak pull-up
TEST4 F4 Input, LVCMOS Weak pull-up Reserved TI test pin. During normal (non-test-mode) operation, this pin is configured as an input and therefore is not affected by the presence of a signal. This pin should be tied to GND or left floating.
TEST5 E4 Input, LVCMOS Weak pull-up Reserved TI test pin. During normal (non-test-mode) operation, this pin is configured as an input and therefore is not affected by the presence of a signal. This pin may be left floating, tied to GND, or connected to a 2.5V (max) output.
TEST6 D4 Input, LVCMOS Weak pull-up
TEST7 D12 Input, LVCMOS Weak pull-up
POWER
VDD D6, D8, D10, E5, E6, E7, E8, E9, E10, F6, F8, F10 Power None Power supply, VDD = 2.5V ±5%. TI recommends connecting at least six de-coupling capacitors between the Retimer’s VDD plane and GND as close to the Retimer as possible. For example, four 0.1μF capacitors and two 1μF capacitors directly beneath the device or as close to the VDD pins as possible.
The VDD pins on this device should be connected through a low-resistance path to the board VDD plane.
GND A1, A2, A4, A6, A8, A10, A12, A14, A15, B2, B4, B6, B8, B10, B12, B14, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, D1, D2, D5, D7, D9, D11, D14, D15, E11, F1, F2, F5, F7, F9, F11, F14, F15, G2, G3, G4, G5, G6, G7, G8, G9, G10, G11, G12, G13, G14, H2, H4, H6, H8, H10, H12, H14, J1, J2, J4, J6, J8, J10, J12, J14, J15 Power None Ground reference. The GND pins on this device should be connected through a low-resistance path to the board GND plane.