SNLS538B September   2016  – February 2024 DS280DF810

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements, Retimer Jitter Specifications
    7. 5.7  Timing Requirements, Retimer Specifications
    8. 5.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 5.9  Recommended SMBus Switching Characteristics (Target Mode)
    10. 5.10 Recommended SMBus Switching Characteristics (Controller Mode)
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Data Path Operation
        1. 6.3.1.1 AC-Coupled Receiver and Transmitter
        2. 6.3.1.2 Signal Detect
        3. 6.3.1.3 Continuous Time Linear Equalizer (CTLE)
        4. 6.3.1.4 Variable Gain Amplifier (VGA)
        5. 6.3.1.5 2x2 Cross-Point Switch
        6. 6.3.1.6 Decision Feedback Equalizer (DFE)
        7. 6.3.1.7 Clock and Data Recovery (CDR)
        8. 6.3.1.8 Calibration Clock
        9. 6.3.1.9 Differential Driver with FIR Filter
          1. 6.3.1.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
          2. 6.3.1.9.2 Output Driver Polarity Inversion
      2. 6.3.2 Debug Features
        1. 6.3.2.1 Pattern Generator
        2. 6.3.2.2 Pattern Checker
        3. 6.3.2.3 Eye Opening Monitor
        4. 6.3.2.4 Interrupt Signals
    4. 6.4 Device Functional Modes
      1. 6.4.1 Supported Data Rates
      2. 6.4.2 SMBus Controller Mode
      3. 6.4.3 42
      4. 6.4.4 Device SMBus Address
    5. 6.5 Programming
      1. 6.5.1 Bit Fields in the Register Set
      2. 6.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 6.6 Register Maps
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Backplane and Mid-Plane Reach Extension Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Front-Port Jitter Cleaning Application
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABW|135
  • ABV|135
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.3.1.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization

The output differential voltage (VOD) of the driver is controlled by manipulating the FIR tap settings. The main cursor tap is the primary knob for amplitude adjustment. The pre and post cursor FIR tap settings can then be adjusted to provide equalization. To maintain a constant peak-to-peak VOD, the user should adjust the main cursor tap value relative to the pre tap or post tap changes so as to maintain a constant absolute sum of the FIR tap values. The table below shows various settings for VOD settings ranging from 205 mVpp to 1225 mVpp (typical). Note that the output peak-to-peak amplitude is a function of the sum of the absolute values of the taps, whereas the low-frequency amplitude is purely a function of the main-cursor value.

Table 6-2 Typical VOD and FIR Values
FIR SETTINGSPEAK-TO PEAK VOD(V)RPRE(dB)RPST(dB)
PRE-CURSOR:
REG_0x3E[6:0]		MAIN-CURSOR:
REG_0x3D[6:0]		POST-CURSOR:
REG_0x3F[6:0]
0000.205NANA
0+100.260NANA
0+200.305NANA
0+300.355NANA
0+400.395NANA
0+500.440NANA
0+600.490NANA
0+700.525NANA
0+800.565NANA
0+900.610NANA
0+1000.650NANA
0+1100.685NANA
0+1200.720NANA
0+1300.760NANA
0+1400.790NANA
0+1500.825NANA
0+1600.860NANA
0+1700.890NANA
0+1800.925NANA
0+1900.960NANA
0+2000.985NANA
0+2101.010NANA
0+2201.040NANA
0+2301.075NANA
0+2401.095NANA
0+2501.125NANA
0+2601.150NANA
0+2701.165NANA
0+2801.190NANA
0+2901.205NANA
0+3001.220NANA
0+3101.225NANA
0+18-10.960NA2.1
0+17-20.960NA2.5
0+16-30.960NA3.1
0+15-40.960NA3.8
0+14-50.960NA4.7
0+13-60.960NA5.8
0+12-70.960NA7.2
0+11-80.960NA9.0
0+10-90.960NA11.6
-11800.9601.0NA
-21700.9601.6NA
-31600.9602.4NA
-41500.9603.3NA
026-11.165NA1.1
025-21.165NA1.3
024-31.165NA1.8
023-41.165NA2.2
022-51.165NA2.7
021-61.165NA3.3
020-71.165NA3.9
019-81.165NA4.7
018-91.165NA5.7
017-101.165NA6.9
016-111.165NA8.4
015-121.165NA10.1
-12601.1650.7NA
-22501.1651.2NA
-32401.1651.5NA
-42301.1652.0NA
-52201.1652.6NA
-62101.1653.2NA
-72001.1654.0NA

The recommended pre-cursor and post-cursor settings for a given channel will depend on the channel characteristics (mainly insertion loss) as well as the equalization capabilities of the downstream receiver. The DS280DF810 receiver, with its highly-capable CTLE and DFE, does not require a significant amount of pre-cursor or post-cursor. The figures below give general recommendations for pre- and post-cursor for different channel loss conditions. The insertion loss (IL) in these plots refers to the total loss between the link partner transmitter and the DS280DF810 receiver.

GUID-8E212883-7B53-4252-A184-CE1BE892643B-low.gifFigure 6-7 Guideline for Link partner FIR Settings When IL ≤ 15dB
GUID-21366545-2ACF-4B6F-81AA-36A0930E6372-low.gifFigure 6-8 Guideline for Link partner FIR Settings When IL ≤ 25dB
GUID-56758477-A3FB-43A7-8D34-90F57580100C-low.gifFigure 6-9 Guideline for Link partner FIR Settings When IL ≤ 35dB