SNLS538B September   2016  – February 2024 DS280DF810

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements, Retimer Jitter Specifications
    7. 5.7  Timing Requirements, Retimer Specifications
    8. 5.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 5.9  Recommended SMBus Switching Characteristics (Target Mode)
    10. 5.10 Recommended SMBus Switching Characteristics (Controller Mode)
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Data Path Operation
        1. 6.3.1.1 AC-Coupled Receiver and Transmitter
        2. 6.3.1.2 Signal Detect
        3. 6.3.1.3 Continuous Time Linear Equalizer (CTLE)
        4. 6.3.1.4 Variable Gain Amplifier (VGA)
        5. 6.3.1.5 2x2 Cross-Point Switch
        6. 6.3.1.6 Decision Feedback Equalizer (DFE)
        7. 6.3.1.7 Clock and Data Recovery (CDR)
        8. 6.3.1.8 Calibration Clock
        9. 6.3.1.9 Differential Driver with FIR Filter
          1. 6.3.1.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
          2. 6.3.1.9.2 Output Driver Polarity Inversion
      2. 6.3.2 Debug Features
        1. 6.3.2.1 Pattern Generator
        2. 6.3.2.2 Pattern Checker
        3. 6.3.2.3 Eye Opening Monitor
        4. 6.3.2.4 Interrupt Signals
    4. 6.4 Device Functional Modes
      1. 6.4.1 Supported Data Rates
      2. 6.4.2 SMBus Controller Mode
      3. 6.4.3 42
      4. 6.4.4 Device SMBus Address
    5. 6.5 Programming
      1. 6.5.1 Bit Fields in the Register Set
      2. 6.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 6.6 Register Maps
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Backplane and Mid-Plane Reach Extension Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Front-Port Jitter Cleaning Application
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABW|135
  • ABV|135
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Rbaud Input data rate Full-rate 20.2 28.4 Gbps
Half-rate 10.1 14.2 Gbps
Quarter-rate 5.05 7.1 Gbps
tEEPROM EEPROM configuration load time Single device reading its configuration from an EEPROM. Common channel configuration. This time scales with the number of devices reading from the same EEPROM. 15(2) ms
tEEPROM EEPROM configuration load time Single device reading its configuration from an EEPROM. Unique channel configuration. This time scales with the number of devices reading from the same EEPROM. 40(2) ms
tPOR Power-on reset assertion time Internal power-on reset (PoR) stretch between stable power supply and de-assertion of internal PoR. The SMBus address is latched on the completion of the PoR stretch, and SMBus accesses are permitted. 50 ms
POWER SUPPLY
Wchannel Power consumption per active channel With CTLE, full DFE, Tx FIR, Driver, and Cross-point enabled. Idle power consumption is not included. 241 305 mW
With CTLE, full DFE, Tx FIR, and Driver enabled; Cross-point disabled. Idle power consumption is not included. 233 mW
With CTLE, partial DFE (taps 1-2 only), Tx FIR, and Driver enabled; Cross-point and DFE taps 3-5 disabled. Idle power consumption is not included. 220 mW
With CTLE, Tx FIR, Driver, and Cross-point enabled; DFE disabled. Idle power consumption is not included. 211 290 mW
Assuming CDR acquiring lock with CTLE, full DFE, Tx FIR, Driver, and Cross-point enabled. Idle power consumption is not included. 365 430 mW
Assuming CDR acquiring lock with CTLE, Tx FIR, Driver, and Cross-point enabled; DFE disabled. Idle power consumption is not included. 318 393 mW
PRBS checker power consumption only(1) 220 302 mW
PRBS generator power consumption only(1) 230 315 mW
Wstatic_total Total idle power consumption Idle or static mode, power supplied, no high-speed data present at inputs, all channels automatically powered down. 658 1050 mW
Itotal Active mode total device supply current consumption With CTLE, full DFE, Tx FIR, Driver, and Cross-point enabled. 1036 1330 mA
With CTLE, full DFE, Tx FIR, and Driver enabled; Cross-point disabled. 1010 mA
With CTLE, partial DFE (taps 1-2 only), Tx FIR, and Driver enabled; Cross-point and DFE taps 3-5 disabled. 970 mA
With CTLE, Tx FIR, Driver, and Cross-point enabled. DFE disabled. 940 1278 mA
Istatic_total Idle mode total device supply current consumption Idle or static mode. Power supplied, no high-speed data present at inputs, all channels automatically powered down. 263 400 mA
LVCMOS DC SPECIFICATIONS
VIH Input high level voltage 2.5V LVCMOS pins 1.75 VDD V
3.3V LVCMOS pin (READ_EN_N) 1.75 3.6 V
VIL Input low level voltage 2.5V LVCMOS pins GND 0.7 V
3.3V LVCMOS pin (READ_EN_N) GND 0.8 V
VTH High level (1) input voltage 4-level pins ADDR0, ADDR1, and EN_SMB 0.95 * VDD V
Float level input voltage 4-level pins ADDR0, ADDR1, and EN_SMB 0.67 * VDD V
10 K to GND input voltage 4-level pins ADDR0, ADDR1, and EN_SMB 0.33 * VDD V
Low level (0) input voltage 4-level pins ADDR0, ADDR1, and EN_SMB 0.1 V
VOH High level output voltage IOH = 4 mA 2 V
VOL Low level output voltage IOL = -4 mA 0.4 V
IIH Input high leakage current Vinput = VDD, Open drain pins 70 μA
IIH Input high leakage current Vinput = VDD and CAL_CLK_IN pin 65 μA
IIH Input high leakage current Vinput = VDD, ADDR[1:0] and EN_SMB pins 120 μA
IIH Input high leakage current Vinput = VDD, READ_EN_N 75 μA
IIL Input low leakage current Vinput = 0V, Open drain pins -15 μA
IIL Input low leakage current Vinput = 0V, CAL_CLK_IN pins -45 μA
IIL Input low leakage current Vinput = 0V, ADDR[1:0], READ_EN_N, and EN_SMB pins -230 μA
RECEIVER INPUTS (RXnP, RXnN)
VIDMax Maximum input differential voltage For normal operation 1225 mVppd
RLSDD11 Differential input return loss, SDD11 Between 50MHz and 3.69GHz <-16 dB
RLSDD11 Differential input return loss, SDD11 Between 3.69GHz and 12.9GHz <-12 dB
RLSDC11 Differential to common-mode input return loss, SDC11 Between 50MHz and 12.9GHz <-23 dB
RLSCD11 Differential to common-mode input return loss, SCD11 Between 50MHz and 12.9GHz <-24 dB
RLSCC11 Common-mode input return loss, SCC11 Between 150MHz and 10GHz <-10 dB
RLSCC11 Common-mode input return loss, SCC11 Between 10GHz and 12.9GHz <-10 dB
VSDAT AC signal detect assert (ON) threshold level Minimum input peak-to-peak amplitude level at device pins required to assert signal detect. 25.78125Gbps with PRBS7 pattern and 20dB loss channel 196 mVppd
VSDDT AC signal detect de-assert (OFF) threshold level Maximum input peak-to-peak amplitude level at device pins which causes signal detect to de-assert. 25.78125Gbps with PRBS7 pattern and 20dB loss channel 147 mVppd
TRANSMITTER OUTPUTS (TXnP, TXnN)
VOD Output differential voltage amplitude Measured with c(0)=7 setting (Reg_0x3D[6:0]=0x07, Reg_0x3E[6:0]=0x40, REG_0x3F[6:0]=0x40). Differential measurement using an 8T pattern (eight 1 s followed by eight 0 s) at 25.78125Gbps with TXPn and TXNn terminated by 50Ω to GND. 525 mVppd
VOD Output differential voltage amplitude Measured with c(0)=31 setting (Reg_0x3D[6:0]=0x1F, Reg_0x3E[6:0]=0x40, REG_0x3F[6:0]=0x40). Differential measurement using an 8T pattern (eight 1 s followed by eight 0 s) at 25.78125Gbps with TXPn and TXNn terminated by 50Ω to GND. 1225 mVppd
VODidle Differential output amplitude with TX disabled < 11 mVppd
VODres Output VOD resolution Difference in VOD between two adjacent c(0) settings. Applies to VOD in the 525mVppd to 1225mVppd range [c(0)>4]. < 50 mVppd
Vcm-TX-AC Common-mode AC output noise With respect to signal ground. Measured with PRBS9 data pattern. Measured with a 33GHz (-3dB) low-pass filter. 6.5 mV, RMS
tr, tf Output transition time 20%-to-80% rise time and 80%-to-20% fall time on a clock-like {11111 00000} data pattern at 25.78125Gbps. Measured for ~800mVppd output amplitude and no equalization: Reg_0x3D=+13, Reg_0x3E=0, REG_0x3F=0 17 ps
RLSDD22 Differential output return loss, SDD22 Between 50MHz and 5GHz <-12 dB
RLSDD22 Differential output return loss, SDD22 Between 5GHz and 12.9GHz <-9 dB
RLSCD22 Common-mode to differential output return loss, SCD22 Between 50MHz and 12.9GHz <-22 dB
RLSDC22 Differential-to-common-mode output return loss, SDC22 Between 50MHz and 12.9GHz <-22 dB
RLSCC22 Common-mode output return loss, SCC22 Between 50MHz and 10GHz <-9 dB
RLSCC22 Common-mode output return loss, SCC22 Between 10GHz and 12.9GHz <-9 dB
SMBus ELECTRICAL CHARACTERISTICS (SLAVE MODE)
VIH Input high level voltage SDA and SDC 1.75 3.6 V
VIL Input low level voltage SDA and SDC GND 0.8 V
CIN Input pin capacitance 15 pF
VOL Low level output voltage SDA or SDC, IOL = 1.25 mA 0.4 V
IIN Input current SDA or SDC, VINPUT = VIN, VDD, GND -15 15 μA
TR SDA rise time, read operation Pull-up resistor = 1kΩ, Cb = 50pF 150 ns
TF SDA fall time, read operation Pull-up resistor = 1kΩ, Cb = 50pF 4.5 ns
(1) For optimal performance, it is recommended to not enable more than two PRBS blocks (checker or generator) per channel quad.
(2) From low assertion of READ_EN_N to low assertion of ALL_DONE_N. Does not include Power-On Reset time.