SNLS538B September   2016  – February 2024 DS280DF810

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements, Retimer Jitter Specifications
    7. 5.7  Timing Requirements, Retimer Specifications
    8. 5.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 5.9  Recommended SMBus Switching Characteristics (Target Mode)
    10. 5.10 Recommended SMBus Switching Characteristics (Controller Mode)
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Data Path Operation
        1. 6.3.1.1 AC-Coupled Receiver and Transmitter
        2. 6.3.1.2 Signal Detect
        3. 6.3.1.3 Continuous Time Linear Equalizer (CTLE)
        4. 6.3.1.4 Variable Gain Amplifier (VGA)
        5. 6.3.1.5 2x2 Cross-Point Switch
        6. 6.3.1.6 Decision Feedback Equalizer (DFE)
        7. 6.3.1.7 Clock and Data Recovery (CDR)
        8. 6.3.1.8 Calibration Clock
        9. 6.3.1.9 Differential Driver with FIR Filter
          1. 6.3.1.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
          2. 6.3.1.9.2 Output Driver Polarity Inversion
      2. 6.3.2 Debug Features
        1. 6.3.2.1 Pattern Generator
        2. 6.3.2.2 Pattern Checker
        3. 6.3.2.3 Eye Opening Monitor
        4. 6.3.2.4 Interrupt Signals
    4. 6.4 Device Functional Modes
      1. 6.4.1 Supported Data Rates
      2. 6.4.2 SMBus Controller Mode
      3. 6.4.3 42
      4. 6.4.4 Device SMBus Address
    5. 6.5 Programming
      1. 6.5.1 Bit Fields in the Register Set
      2. 6.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 6.6 Register Maps
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Backplane and Mid-Plane Reach Extension Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Front-Port Jitter Cleaning Application
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABW|135
  • ABV|135
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.2 Detailed Design Procedure

The design procedure for front-port applications is as follows:

  1. Determine the total number of channels on the board which require a DS280DF810 for signal conditioning. This will dictate the total number of DS280DF810 devices required for the board. It is generally recommended that channels with similar total insertion loss on the board be grouped together in the same DS280DF810 device. This will simplify the device settings, as similar loss channels generally utilize similar settings.
  2. Determine the maximum current draw required for all DS280DF810 retimers. This may impact the selection of the regulator for the 2.5V supply rail. To calculate the maximum current draw, multiply the maximum transient power supply current by the total number of DS280DF810 devices.
  3. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two ways to approach this calculation:
    1. Maximum mission-mode operational power consumption is when all channels are locked and retransmitting the data which is received. PRBS pattern checkers and generators are not used in this mode since normal traffic cannot be checked with a PRBS checker. For this calculation, multiply the worst-case power consumption in mission mode by the total number of DS280DF810 devices.
    2. Maximum debug-mode operational power consumption is when all channels are locked and retransmitting the data which is received. At the same time, some channels’ PRBS checkers or generators may be enabled. For this calculation, multiply the worst-case power consumption in debug mode by the total number of DS280DF810 devices.
  4. Determine the SMBus address scheme needed to uniquely address each DS280DF810 device on the board. Each DS280DF810 can be strapped with one of 16 unique SMBus addresses. If there are more DS280DF810 devices on the board than the number of unique SMBus addresses which can be assigned, then use an I2C expander like the TCA/PCA family of I2C/SMBus switches and multiplexers to split up the SMBus into multiple busses.
  5. Determine if the device will be configured from EEPROM (SMBus Controller Mode) or from the system I2C bus (SMBus Target Mode).
    1. If SMBus Controller Mode will be used, provisions should be made for an EEPROM on the board with 8-bit SMBus address 0xA0.
    2. If SMBus Target Mode will be used for all device configurations, an EEPROM is not needed.
  6. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD supply and GND. Refer to the pin function description in Section 4 for more details.
  7. Make provisions in the schematic and layout for a 25MHz (±100 ppm) single-ended CMOS clock. Each DS280DF810 retimer buffers the clock on the CAL_CLK_IN pin and presents the buffered clock on the CAL_CLK_OUT pin. This allows multiple (up to 20) retimers’ calibration clocks to be daisy chained to avoid the need for multiple oscillators on the board. If the oscillator used on the board has a 2.5V CMOS output, then no AC coupling capacitor or resistor ladder is required at the input to CAL_CLK_IN. No AC coupling or resistor ladder is needed between one retimer’s CAL_CLK_OUT output and the next retimer’s CAL_CLK_IN input. The final retimer’s CAL_CLK_OUT output can be left floating.
  8. Connect the INT_N open-drain output to an FPGA or CPU if interrupt monitoring is desired. Note that multiple retimers’ INT_N outputs can be connected together since this is an open-drain output. The common INT_N net should be pulled high.
  9. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in Section 5.6, care should be taken so that the operating junction temperature is met as well as the CDR stay-in-lock ambient temperature range defined in Section 5.6. For example, if initial CDR lock acquisition occurs at an ambient temperature of 85 °C, then maintaining CDR lock would require the ambient temperature surrounding the DS280DF810 to be kept above (85 °C - TEMPLOCK-).