SNLS542C October   2016  – December 2020 DS280MB810

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements – Serial Management Bus Interface
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Data Path Operation
      2. 8.3.2 AC-coupled Receiver Inputs
      3. 8.3.3 Signal Detect
      4. 8.3.4 2-Stage CTLE
      5. 8.3.5 Driver DC Gain Control
      6. 8.3.6 2x2 Cross-point Switch
      7. 8.3.7 Configurable SMBus Address
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Slave Mode Configuration
      2. 8.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 8.5 Programming
      1. 8.5.1 Transfer of Data with the SMBus Interface
    6. 8.6 Register Maps
      1. 8.6.1 Register Types: Global, Shared, and Channel
      2. 8.6.2 Global Registers: Channel Selection and ID Information
      3. 8.6.3 Shared Registers
      4. 8.6.4 Channel Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Backplane and Mid-Plane Reach Extension
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Front-Port Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Pattern Generator Characteristics
        2. 9.2.3.2 Equalizing Moderate Pre-Channel Loss
        3. 9.2.3.3 Equalizing High Pre-Channel Loss
        4. 9.2.3.4 Equalizing High Pre-Channel Loss and Moderate Post-Channel Loss
    3. 9.3 Initialization Set Up
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
      1. 11.2.1 Stripline Example
      2. 11.2.2 Microstrip Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.3.4 Equalizing High Pre-Channel Loss and Moderate Post-Channel Loss

This example application result demonstrates the DS280MB810 equalizing for pre-channel and post-channel insertion loss introduced by FR4 channels.

GUID-19F6B17C-4F0F-4AE7-AA3B-1C35A9C51572-low.gifFigure 9-19 10 in input channel and 5 in output channel test setup
GUID-0F20145A-5371-4AE0-9B92-46C946E4E7B6-low.pngFigure 9-20 25.78125 Gbps Eye Diagram with 10 in input channel and 5 in output channel, Linear mode
GUID-8936D186-7053-42CC-A6DF-87299D8B4F78-low.pngFigure 9-21 10.3125 Gbps nPPI Eye Mask with 10 in input channel and 5 in output channel
Table 9-4 Settings and Measurements for CAUI-4 and nPPI with 10 in input channel and 5 in output channel
25.78125 Gbps (CAUI-4)10.3125 Gbps (nPPI)
Transmission Line 110 in 5 mil FR4 + 8 in SMA cable10 in 5 mil FR4 + 8 in SMA cable
Transmission Line 25 in 5 mil FR4 + 8 in SMA cable5 in 5 mil FR4 + 8 in SMA cable
DS280MB810 Rx Channel Loss22 dB @ 12.9 GHz10 dB @ 5.2 GHz
DS280MB810 Tx Channel Loss14.5 dB @ 12.9 GHz6 dB @ 5.2 GHz
EQ BST177
EQ BST277
EQ BW33
VOD32
EQ DC Gain ModeLowLow
Total Jitter @ 1E-1514.8 psP-P17.0 psP-P
Differential Eye Height @ 1E-1567 mVP-P407 mVP-P
Mask violationsN/A0