SNLS683 june   2023 DS320PR1601

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD and Latchup Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Five-Level Control Inputs
      5. 7.3.5 Integrated Capacitors
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
  9. Programming
    1. 8.1 Pin Configurations for Lanes
    2. 8.2 SMBUS/I2C Register Control Interface
      1. 8.2.1 Shared Registers
      2. 8.2.2 Channel Registers
    3. 8.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 PCIe x16 Lane Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application Curves

The DS320PR1601 is a linear redriver that can be used to extend channel reach of a PCIe link. Normally, PCIe-compliant Tx and Rx are equipped with signal-conditioning functions and can handle channel losses of up to 36 dB at 32 Gbps (16 GHz) PCIe 5.0. With the DS320PR1601, the total channel loss between a PCIe root complex and an end point can be extended up to 52 dB (18 dB additional) at 16 GHz.

To demonstrate the reach extension capability of the DS320PR1601, two comparative setups are constructed. In first setup as shown in Figure 9-3 there is no redriver in the PCIe 5.0 link. Figure 9-4 shows eye diagram at the end of the link using SigTest. In second setup as shown in Figure 9-5, the DS320PR1601 is inserted in the middle to extend link reach. Figure 9-6 shows SigTest eye diagram.

GUID-20230201-SS0I-CP7T-PTQD-XJQKPPQWJPNF-low.svgFigure 9-3 PCIe 5.0 Link Baseline Setup Without Redriver – the Link Elements
GUID-20230525-SS0I-B9JM-CRJB-FHC2D69H3RCP-low.svgFigure 9-5 PCIe 5.0 Link Setup with the DS320PR1601 – the Link Elements
GUID-20230526-SS0I-JNBB-WGXR-CN0KM7TLBRP7-low.pngFigure 9-4 PCIe 5.0 link Baseline Setup Without Redriver – Eye Diagram Using SigTest
GUID-20230526-SS0I-KBMV-VCT8-8RZ3HSWCM3MT-low.pngFigure 9-6 PCIe 5.0 Link Setup with the DS320PR1601 – Eye Diagram Using SigTest

Table 9-1 provides the PCIe 5.0 links without and with the DS320PR1601. The illustration shows that redriver is capable of ≅18 dB (additional) reach extension at PCIe 5.0 speed with EQ = 12 (15 dB) and flat_gain = 011 (-1.2 dB). Note: actual reach extension depends on various signal integrity factors. It is recommended to run signal integrity simulations with all the components in the link to get any guidance.

Table 9-1 PCIe 5.0 Reach Extension Using the DS320PR1601
Setup Pre Channel Loss Post Channel Loss Total Loss Eye at BER 1E-12 SigTest Pass?
Baseline – no DUT 36 dB 13.0 ps, 27.8 mV Pass
With DUT (DS320PR1601) 27 dB 25 dB 52 dB 13.5 ps, 31.2 mV Pass