SNLS683
june 2023
DS320PR1601
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD and Latchup Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
DC Electrical Characteristics
6.6
High Speed Electrical Characteristics
6.7
SMBUS/I2C Timing Characteristics
6.8
Typical Characteristics
6.9
Typical Jitter Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Linear Equalization
7.3.2
Flat-Gain
7.3.3
Receiver Detect State Machine
7.3.4
Five-Level Control Inputs
7.3.5
Integrated Capacitors
7.4
Device Functional Modes
7.4.1
Active PCIe Mode
7.4.2
Active Buffer Mode
7.4.3
Standby Mode
8
Programming
8.1
Pin Configurations for Lanes
8.2
SMBUS/I2C Register Control Interface
8.2.1
Shared Registers
8.2.2
Channel Registers
8.3
SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
PCIe x16 Lane Configuration
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
ZDG|354
MPBGAV1C
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snls683_oa
snls683_pm
1
Features
16-lane linear redriver supporting
PCIe®
5.0, CXL 2.0, CCIX
, and UPI 2.0
Supports data rates up to
32
-Gbps
Intel retimer common footprint compatible
64 integrated AC coupling capacitors on Tx pins inside package saving board space
CTLE boosts of
21 dB at 16 GHz
Ultra-low latency of 130 ps
Low additive random jitter of
50
fs for PRBS data
Single 3.3 V supply
Low active power of 164 mW/channel
I
2
C/SMBus or EEPROM programming
Automatic receiver detection for PCIe use cases
Seamless support for PCIe link training
Internal voltage regulator provides immunity to supply noise
Support for x4, x8, x16 bus width
8.90 mm × 22.80 mm BGA package