SNLS683 june   2023 DS320PR1601

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD and Latchup Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Five-Level Control Inputs
      5. 7.3.5 Integrated Capacitors
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
  9. 8 Programming
    1. 8.1 Pin Configurations for Lanes
    2. 8.2 SMBUS/I2C Register Control Interface
      1. 8.2.1 Shared Registers
      2. 8.2.2 Channel Registers
    3. 8.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 PCIe x16 Lane Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 High Speed Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Receiver
RLRX-DIFF Input differential return loss 50 MHz -32 dB
4 GHz -22 dB
8 GHz -14 dB
16 GHz -9 dB
RLRX-CM Input common-mode return loss 50 MHz -24 dB
4 GHz -18 dB
8 GHz -14 dB
16 GHz -8 dB
XTRX Receive-side pair-to-pair isolation Pair-to-pair isolation (SDD21) between two adjacent receiver pairs from 10 MHz to 16 GHz. -50 dB
Transmitter
VTX-AC-CM-PP Tx AC peak-to-peak common mode voltage Measured with lowest EQ, flat_gain = 101 50 mVpp
VTX-RCV-DETECT Amount of voltage change allowed during receiver detection Measured while Tx is sensing whether a low-impedance receiver is present. No load is connected to the driver output 0 600 mV
RLTX-DIFF Output differential return loss 50 MHz -30 dB
4 GHz -14 dB
8 GHz -11 dB
16.0 GHz -9 dB
RLTX-CM Output common-mode return loss 50 MHz -22 dB
4 GHz -16 dB
8 GHz -8 dB
16 GHz  -8 dB
XTTX Transmit-side pair-to-pair isolation Minimum pair-to-pair isolation (SDD21) between two adjacent transmitter pairs from 10 MHz to 16 GHz. -45 dB
CAC,TX AC coupling capacitors on transmit pins (integrated inside device package) 220 nF
Device Datapath
TPLHD/PHLD Input-to-output latency (propagation delay) through a data channel For either Low-to-High or High-to-Low transition.  130 170 ps
LTX-SKEW Lane-to-Lane Output Skew Between any two lanes within a single transmitter.  24 ps
TRJ-DATA Additive random jitter with data Jitter through redriver minus the calibration trace. 32 Gbps PRBS15. 800 mVpp-diff input swing. 50 fs
TRJ-INTRINSIC Intrinsic additive random jitter with clock  Jitter through redriver minus the calibration trace. 16 GHz CK. 800 mVpp-diff input swing. 30 fs
JITTERTOTAL-DATA Additive total jitter with data Jitter through redriver minus the calibration trace. 32 Gbps PRBS15. 800 mVpp-diff input swing. 2.3 ps
JITTERTOTAL-INTRINSIC Intrinsic additive total jitter with clock Jitter through redriver minus the calibration trace. 16 GHz CK. 800 mVpp-diff input swing. 1 ps
EQ-MIN16G EQ boost at min setting (EQ INDEX = 0) AC gain at 16 GHz relative to gain at 100 MHz.  2.9 dB
EQ-MAX16G EQ boost at max setting (EQ INDEX = 19) AC gain at 16 GHz relative to gain at 100 MHz.  21 dB
FLAT-GAINVAR Flat gain variation across PVT measured at DC Flat_gain = 000, 001, 011, 101 or 111, at minimum EQ setting. Max-Min for a single channel.  -1.0 1.0 dB
EQ-GAINVAR,16G EQ boost variation across PVT At 16 GHz. Flat_gain = 101, maximum EQ setting. Max-Min.  -4 3 dB
LINEARITY-DC Output DC linearity Flat_gain = 101. 128T pattern at 2.5 Gbps. 1800 mVpp
LINEARITY-AC Output AC linearity Flat_gain = 101. 1T pattern at 32 Gbps. 770 mVpp