SNLS739 October   2023 DS320PR410

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Pin mode
        1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
        1. 7.5.2.1 Shared Registers
        2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe Reach Extension – x16 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNQ|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application Curves

The DS320PR410 is a linear redriver that can be used to extend channel reach of a PCIe link. Normally, PCIe-compliant Tx and Rx are equipped with signal-conditioning functions and can handle channel losses of up to 36 dB at 16 GHz. With the DS320PR410, the total channel loss between a PCIe root complex and an end point can be extended up to 58 dB at 16 GHz.

To demonstrate the reach extension capability of the DS320PR410, two comparative setups are constructed. In first setup as shown in Figure 8-3 there is no redriver in the PCIe 5.0 link. Figure 8-4 shows eye diagram at the end of the link using SigTest. In second setup as shown in Figure 8-5, the DS320PR410 is inserted in the middle to extend link reach. Figure 8-6 shows SigTest eye diagram.

GUID-20231005-SS0I-WHPG-QZGQ-GHS2RGFJXF1L-low.svgFigure 8-3 PCIe 5.0 Link Baseline Setup Without Redriver the Link Elements
GUID-20230822-SS0I-CBXZ-4NKP-XHSHRRWT47JP-low.svgFigure 8-5 PCIe 5.0 Link Setup with the DS320PR410 the Link Elements
GUID-20231005-SS0I-DZ6C-6NN4-NNPNKQPCLHH5-low.pngFigure 8-4 PCIe 5.0 link Baseline Setup Without Redriver Eye Diagram Using SigTest
GUID-20231005-SS0I-VFS8-L55R-JJHHR2ZV5BSJ-low.pngFigure 8-6 PCIe 5.0 Link Setup with the DS320PR410 Eye Diagram Using SigTest

Table 8-1 provides the PCIe 5.0 links without and with the DS320PR410 that shows that redriver is capable of ≅22 dB reach extension at PCIe 5.0 speed. Note: actual reach extension depends on various signal integrity factors. It is recommended to run signal integrity simulations with all the components in the link to get more accurate guidance.

Table 8-1 PCIe 5.0 Reach Extension Using the DS320PR410
SetupPre Channel LossPost Channel LossTotal LossEye at BER 1E-12SigTest Pass?
Baseline – no DUT≅36 dB13 ps, 28 mVPass
With DUT (DS320PR410)≅29 dB≅29 dB≅58 dB13 ps, 35 mVPass